AZ100EP16FE Datasheet, PDF (1/5 Pages) Arizona Microtek, Inc – ECL/PECL High Speed VCSEL Driver with Variable Output Swing or Limiting Amplifier

AZ100EP16FE
ARIZONA MICROTEK, INC.
ECL/PECL High Speed VCSEL Driver with
Variable Output Swing or Limiting Amplifier
FEATURES
• Silicon-Germanium for High Speed
Operation
• <100ps Typical Rise/Fall Times
• Optimized for 0.622 to 2.5Gbps
Fiber Applications
• S-Parameter (.s2p) and IBIS Model
Files available on Arizona Microtek
Website
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER MARKING NOTES
TSSOP 8
AZ100EP16FET
AZHP
16FE
1,2
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2 Date code on underside of part. Format: “Y” or “YY” for year followed by “WW”
for week.
DESCRIPTION
The AZ100EP16FE is a Silicon–Germanium (SiGe) differential VCSEL driver with variable output swing or
limiting post amplifier. The 100EP16FE is optimized for OC-12, OC-24, OC-48, Ethernet, Sonnet, Fiber Channel or
related applications at data rates up to 2.5Gbps. An input controls the amplitude of the Q/Q¯ outputs, which allows
compensation for differing VCSEL characteristics.
The operational range of the 100EP16FE control input, V_CTRL, is from V_REF (full swing) to V_CC (small swing).
For post amplifier applications, maximum swing is achieved by leaving the V_CTRL pin open or by tying it to the
negative supply pin (V_EE). Simple control of the output swing can be obtained by a variable resistor between the
V_REF and V_CC pins, with the wiper driving V_CTRL. A typical application circuit is described in this Data Sheet.
The 100EP16FE also provides a V_REF output which functions as a DC bias for input AC coupling to the device.
The V_REF pin should be used only as a bias for the 100EP16FE as its current sink/source capability is limited. When
used, the V_REF pin should be bypassed to ground via a 0.01μF capacitor.
The maximum DC output current should be kept below 16mA. Connecting each output (Q/Q¯ ) to V_EE with a
180Ω resistor is typically used. The load is then AC coupled from the output. DC and AC symmetrical loading of
the Q/Q¯ outputs will provide the best output wave shape.
Under open input conditions for D/D¯ , the Q/Q¯ outputs are not guaranteed.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
PIN
D, D¯
V_CTRL
Q, Q¯
V_REF
V_CC
V_EE
FUNCTION
Data Inputs
Output Swing Control
Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
VCTRL
1
2
D
D3
VREF
4
TSSOP 8
8 _VCC
7Q
6Q
5 _VEE
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com