P0340WQLC-T Datasheet, PDF (16/20 Pages) AZ Displays – Tentative Product Specification

32 VCC
33 VSSD
34 NRESET
35 NCS
36 SCL
37 SDA
38 DE
39 VSYNC
40 HSYNC
41 DCLK
42 D27
43 D26
44 D25
45 D24
46 D23
47 D22
48 D21
49 D20
50 D17
51 D16
52 D15
53 D14
54 D13
55 D12
56 D11
57 D10
58 D07
Document No.:
0
1.8V
Normal display
1
2.5V
OTP program
VDC_ENB=1, VDDD is input. (Input range = 1.6V~2.75V)
P ^{A power supply for the Digital circuit. (1.5V~3.6V)}
P ^{Digital ground pin. It must connect to external ground.}
I
Reset pin. Setting either pin low initializes the LSI. Must be reset
after power is supplied. (Normally pull high)
I ^{Serial Interface chip enable pin. (Normally pull high)}
I ^{Serial Interface clock input pin. (Normally pull high)}
I ^{Serial Interface data line. (Normally pull high)}
Data enable:
I When VSYNC+HSYNC+DE mode,
DE=H: Data enable, DE=L: Data disable (Black). (Normally pull low)
Frame synchronizing signal.
I If VSPL=0: Active low.
If VSPL=1: Active high.
Line synchronizing signal.
I If HSPL=0: Active low.
If HSPL=1: Active high.
Dot clock signal.
I _{If DPL=0: Data are input on the rising edge of DOTCLK.}
If DPL=1: Data are input on the falling edge of DOTCLK.
I Digital data input. DX0 is LSB and DX7 is MSB. (Normally pull low)
1. If parallel RGB input mode is used, D0X, D1X, and D2X indicate R,
G, and B data in turn.
2. If serial RGB or RGBD or CCIR601 or CCIR656 input mode is
selected, only D07~D00 are used, and others short to GND.
DX7~DX0 has 8-bit width, respectively to compose 16,777,216
color and 256 gray scale of 1 pixel.
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