G104X1-L01 Datasheet, PDF (14/26 Pages) AZ Displays – TFT LCD Approval Specification

Issued Date: Aug. 26, 2008
Model No.: G104X1-L01
Approval
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Receiver Clock
Item
Symbol Min. Typ. Max. Unit
Frequency
1/Tc
55
65
75 MHZ
Input cycle to
Trcl
-
cycle jitter
-
200 ps
LVDS Receiver Data
Setup Time
Tlvsu 600
-
Hold Time
Tlvhd 600
-
Frame Rate
Fv
50
60
-
ps
-
ps
70
Hz
Total
Vertical Active Display Term _Display
Tv
770
806
950
Th
Tvd
768
768
768
Th
Note
Tv=Tvd+Tvb
-
Blank
Total
Horizontal Active Display Term Display
Blank
Tvb
2
38
182 Th
-
Th 1100 1344 1800 Tc Th=Thd+Thb
Thd 1024 1024 1024 Tc
-
Thb
76
320
776
Tc
-
Note (1) Since this assembly is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this assembly would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd
Tvb
DE
Th
DCLK
DE
DATA
Tc
Thb
Thd
Valid display data (1024 clocks)
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