G104X1-L04 Datasheet, PDF (12/26 Pages) AZ Displays – 10.4” TFT Liquid Crystal Display module

Issued Date: Jan. 04, 2010
Model No.: G104X1-L04
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
DCLK
Item
Frequency
Total
Symbol Min. Typ. Max. Unit
Fc
55
65
75 MHZ
Tv
770
806
950
Th
Vertical Active Display Term
Display
Tvd
768
768
768
Th
Blank
Tvb
2
38
182 Th
Total
Th
1104 ^{1344 1800 Tc}
Horizontal Active Display Term Display
Thd 1024 1024 1024 Tc
Blank
Thb
76
320
776
Tc
Note
Tv=Tvd+Tvb
-
-
Th=Thd+Thb
-
-
Note (1) Since this assembly is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this assembly would operate abnormally.
(2) Frame rate is 60Hz
INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd
Tvb
DE
Th
DCLK
DE
DATA
Tc
Thb
Thd
Valid display data
12/26
Version 2.0