AL4V93 Datasheet, PDF (2/2 Pages) AverLogic Technologies Inc – 16K, 64K-Bit Line FIFO

Input data bus Input
Buffer
WCLK
/WEN
/WRST
Write
Control
Logic
Write Pointer
Offset
Regissers
(2k, 8k) x9
Memory
Array
/OE
Output
Buffer
Output data bus
Read
Control
Logic
Read Pointer
Timing & Logic
Control
RCLK
/REN
/RRST
AL4V9x FIFO Block Diagram
The 9-bit input and output ports operate
independently at a maximum speed of
100MHz. The built-in address decoder and
pointer managing circuits provide a
straightforward bus interface to serially
read/write memory that reduces inter-chip
design efforts. The AL4V9x embedded
memory array and high performance process
technologies with extended controller
functions (read skip, fixed and programmable
status flags... etc.) offer flexible memory
management.
The input data is synchronous with a free-
running clock (WCLK), and input-enable pins
(/WEN). Data is written into the FIFO on
every clock when enable pins are asserted.
The output is synchronous with the other free-
running clock (RCLK) and enables (/REN).
An Output Enable pin (/OE) is provided at the
read port for tri-state control of the output port.
The AL4V9x series are operating in 3.3V
power supply with 5V signal tolerant input.
These chips are available as a 32-pin TQFP
Package.
DISTRIBUTED BY:
AVERLOGIC TECHNOLOGIES, INC. TEL: [phone] e-mail: [e-mail] URL: www.averlogic.com
AVERLOGIC TECHNOLOGIES, CORP. TEL: [phone] e-mail: [e-mail] URL: www.averlogic.com.tw
October 30, 2004