AL5DS9XX9V Datasheet, PDF (1/2 Pages) AverLogic Technologies Inc – 3.3V Synchronous Dual-Port SRAM 4K/8K/16K/32K/64K/128K x 8/9/16/18-bit

AL5DS9xx9V
3.3V Synchronous Dual-Port SRAM
4K/8K/16K/32K/64K/128K x 8/9/16/18-bit
Features
True dual ported memory cells
17 Flow-Through/Pipelined devices:
-- 4K/8K/16K/32K/64K x 18-bit organization (AL5DS9349V/59V/69V/79V/89V)
-- 16K/32K/64K x 16-bit organization (AL5DS9269V/79V/89V)
-- 8K/16K/32K/64K/128K x 9-bit organization (AL5DS9159V/69V/79V/89V/99V)
-- 16K/32K/64K/128K x 8-bit organization (AL5DS9069V/79V/89V/99V)
Supports byte write/read for 16/18 bit devices
Separate upper-byte and lower-byte controls for bus matching (16/18 bit devices only)
3 modes supported:
-Pipelined
-Flow-Through
-Burst
Counter enable and reset
Fast (100-MHz) operation on both ports in Pipelined output mode
Supports depth and width expansion
0.25-micron CMOS for optimum speed / power
High speed clock to data access
3.3V low operating power
Pin-compatible and functionally equivalent to IDT or Cypress
Available in 100 or 128 pin TQFP
Architecture
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ˡ̂̇˸ʳ˄ˍʳ˟˕_˥ʳ˴́˷ʳ˨˕_˥ʳ˴̅˸ʳ˹̂̅ʳʳ˄ˉ˂˄ˋʳ˵˼̇ʳ˷˸̉˼˶˸̆ʳ̂́˿̌ˁ
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ˡ̂̇˸ʳˆˍʳ˔_{˃̑˄˄}ʳ˹̂̅ʳˇ˞ʿʳ˔_{˃̑˄Ë}ʳ˹̂̅ʳˋ˞ʿʳ˔_{˃̑˄ˆ}ʳ˹̂̅ʳ˄ˉ˞ʿʳ˔_{˃̑˄ˇʳ}˹̂̅ʳˆ˅˞ʿʳ˔_{˃̑˄ˈ}ʳ˹̂̅ʳˉˇ˞ʿʳ˴́˷ʳ˔_{˃̑˄ˉ}ʳ˹̂̅ʳ˄˅ˋ˞ʳ˷˸̉˼˶˸̆
AL5DS9xx9V Preliminary Rev: 1.0
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