VMMK-2403 Datasheet, PDF (9/11 Pages) AVAGO TECHNOLOGIES LIMITED – 2 to 4 GHz GaAs High Linearity LNA in Wafer Level Package

Outline Drawing
Top View
0.5 mm
FY
1.00mm
0.8mm
0.7mm
0.3mm
0.2mm
Bottom View
Notes:
1. • indicates pin 1
2. Dimensions are in millimeters
3. Pad Material is minimum 5.0 um thick Au
Side View
Recommended SMT Attachment
The VMMK Packaged Devices are compatible with high
volume surface mount PCB assembly processes.
Manual Assembly for Prototypes
1. Follow ESD precautions while handling packages.
2. Handling should be along the edges with tweezers or
from topside if using a vacuum collet.
3. Recommended attachment is solder paste. Please
see recommended solder reflow profile. Conductive
epoxy is not recommended. Hand soldering is not
recommended.
4. Apply solder paste using either a stencil printer or
dot placement. The volume of solder paste will be
dependent on PCB and component layout and should
be controlled to ensure consistent mechanical and
electrical performance. Excessive solder will degrade RF
performance.
5. Follow solder paste and vendor’s recommendations
when developing a solder reflow profile. A standard
profile will have a steady ramp up from room
temperature to the pre-heat temp to avoid damage
due to thermal shock.
6. Packages have been qualified to withstand a peak
temperature of 260°C for 20 to 40 sec. Verify that the
profile will not expose device beyond these limits.
7. Clean off flux per vendor’s recommendations.
8. Clean the module with Acetone. Rinse with alcohol.
Allow the module to dry before testing.
Suggested PCB Material and Land Pattern
fy the device
rial with one
tal. Soldering
sion than FR5
materials with
ge of the base
evice circuitry
GaAs package
to damaging
s RO4003 and
al and should
1.2 (0.048)
0.400 (0.016)
0.100 (0.004)
0.500 (0.020)
Part of
Input
Circuit
0.200
(0.008)
0.200
(0.008)
0.100 (0.004)
0.500 (0.020)
Part of
Output
Circuit
0.7 (0.028)
ng
source leads
leads of the
unt. The rec-
ern is shown
ned footprint
t borders the
en.
re any plated
ng and tests
hin .003”) and
ure 5 provides
0.076 max
(0.003) 2pl -
see discussion
0.381 (0.015) 2pl
0.254 dia PTH
(0.010) 4pl
Solder Mask
0.400 dia
(0.016) 4pl
N_Fo_igt_ue_rs_e:_{5. Recommended PCB layout for VMMK devices}
1. 0.010” Rogers RO4350
9^Aofs _{tahgeesnoeldraelrrmuales,kifbauVt} ^InAoits
within .004” (100u) of the edge
under the device, then the VIA
should be filled. Any VIA which is covered by the solder
mask and is beyond .004” (100u) of the solder mask edge