English
Language : 

APDS-9190 Datasheet, PDF (9/24 Pages) AVAGO TECHNOLOGIES LIMITED – Digital Proximity Sensor
Interrupts
State Diagram
The interrupt feature of the APDS-9190 simplifies and
improves system efficiency by eliminating the need to
poll the sensor for a light intensity or proximity value. The
interrupt mode is determined by the PIEN or AIEN field in
the ENABLE register.
The APDS-9190 implements four 16-bit-wide interrupt
threshold registers that allow the user to define thresholds
above and below a desired light level. An interrupt can
be generated when the proximity data (PDATA) exceeds
the upper threshold value (PIHTx) or falls below the lower
threshold (PILTx).
The following shows a more detailed flow for the state
machine. The device starts in the sleep mode. The PON
bit is written to enable the device. If the PEN bit is set,
the state machine will step through the proximity states
of proximity accumulate and then proximity ADC con-
version. As soon as the conversion is complete, the state
machine will move to the following state.
If the WEN bit is set, the state machine will then cycle
through the wait state. If the WLONG bit is set, the wait
cycles are extended by 12x over normal operation.
To further control when an interrupt occurs, the
APDS-9190 provides an interrupt persistence feature. This
feature allows the user to specify a number of conver-
sion cycles for which an event exceeding the proximity
interrupt threshold must persist (PPERS) before actually
generating an interrupt. Refer to the register descriptions
for details on the length of the persistence.
PIHTH (r0 x OB), PIHTL (r0 x OA)
APERS (r0 x OC, b3:0)
Prox
Prox Prox
Integration
ADC
Data
Upper Limit
Lower Limit
Prox Persistence
PILTH (r09), PIHTL (r08)
Ch1
Figure 10. Programmable Interrupt
Sleep
PON = 1
PON = 0
Up to 255 LED Pulses
Pulse Frequency: 60 kHz
Time: 16.3 µs – 4.2 ms
Maximum – 4.2 ms
PEN = 1
Prox
Accum
Prox
Check
Start
Wait
Check
WLONG = 1
Counts up to 256 steps
Step: 32.64 ms
Time: 32.64 ms – 8.35 ms
Maximum – 32.64 ms
Wait
Prox
ADC
Up to 255 steps
Step: 2.72 ms
Time: 2.72 ms – 696 ms
Recommended – 2.72 ms 1024 Counts
WEN = 1
WLONG = 0
Counts up to 256 steps
Step: 2.72 ms
Time: 2.72 ms – 696 ms
Maximum – 2.72 ms
Figure 11. Extended State Diagram
9