AMMP-6441 Datasheet, PDF (8/9 Pages) AVAGO TECHNOLOGIES LIMITED – 36-40 GHz, 0.4W Power Amplifi er in SMT Package

Biasing and Operation.
Recommended quiescent DC bias condition for optimum
power and linearity performances is Vd=5 volts with
Vg (-1V) set for Id=450 mA. Minor improvements in
performance are possible depending on the application.
The drain bias voltage range is 3 to 5V. A single DC gate
supply connected to Vg will bias all gain stages. Muting
can be accomplished by setting Vg to the pinch-off
voltage Vp (-2V).
A typical DC biasing connection is shown in Figure 17.
Vg and Vd can be biased from either side. The RF input
port is connected internally to ground; therefore, an input
decoupling capacitor is needed if the preceding output
stage has DC present. The RF output is DC decoupled
internally. No ground wired are needed since ground
connections are made with plated through-holes to the
backside of the device.
Vg
100 pF 0.1 PF 100 pF 0.1 PF
RF Input
1
2
3
8
4
RF Output
7
6
5
100 pF 0.1 PF
Figure 17. Schematic and recommended assemble example
Note: No RF performance degradation is seen due to ESD up to 150V
HBM and 40V MM. The DC characteristics in general show increased
leakage at higher ESD discharge voltages. The user is reminded that this
device is ESD sensitive and needs to be handled with all necessary ESD
protocols.
Notes:
1. Vd may be biased
from either side.
2. Vg may be biased
from either side.
Vd
8