AMGP-6445 Datasheet, PDF (8/9 Pages) AVAGO TECHNOLOGIES LIMITED – ESD protection all ports above 50 V MM and 250 V HBM

Evaluation Board Description
123
GND
GND
AVAGO
Tech
8
AMGP
6445
YWWDNN
5 x 5 mm
4
Q104
GND
GND
765
Demo board circuit
100 pF > 0.1 PF
DET_0
Vdd
123
RF_IN
8
4
765
Vgg _{> 0.1 PF 100 pF}
DET_R
Figure 19.
RF_OUT
Recommended turn on sequence
 Apply Vg1 and Vg2 at -1.5 V
 Apply Vd1 and Vd2 at 0 V
 Increase Vd to 5 V
 Increase Vg of -1.5 V to approximately -0.6 V to obtain
Idsq = 0.7 A
 Apply RF Input not to exceed 20 dBm
Turn off in reverse order
Table 4. Typical Test Conditions
Pin
Vd1,2
5V
Drain Supply Voltage
Idq = Id1 + Id2
700 mA Quiescent Drain Current
Vg1, 2
-0.6
Gate Supply Voltage
Notes:
Vg1 and Vg2 of -0.6 V may need be adjusted to obtain Idsq = 700 mA.
+5 V
100 K:
DET_0
DET_R
Figure 20.
100 K:
10 K:
10 K:
10 K:
10 K:
+5 V
–
+
–5 V
Vout = DET_R – DET_0
Integrated Detector Application Circuit
To obtain temperature compensated RF power detector
function, a differential voltage between DET_R and DET_O
must be obtained by using an operational amplifier in a
differential mode configuration as shown in Figure 19.
8