HCPL-5760 Datasheet, PDF (7/10 Pages) AVAGO TECHNOLOGIES LIMITED – AC/DC to Logic Interface Hermetically Sealed Optocouplers

Typical Characteristics All typical values are at T_A = 25° C, V_CC = 5 V, unless otherwise specified.
Parameter
Symbol Typ.
Units
Test Conditions
Hysteresis
Input Clamp Voltage
Bridge Diode Forward Voltage
Input-Output Resistance
Input-Output Capacitance
Input Capacitance
I_HYS
1.2
mA
V_HYS
1.1
V
V_ILC
-0.76
V
V_D1,2
0.62
V_D3,4
0.73
R_I-O
10¹²

C_I-O
2.0
pF
C_IN
50
pF
I_HYS = I_TH+ – I_TH-
V_HYS = V_TH+ – V_TH-
V_ILC = V₂ - V₃; V₃ = GND;
I_IN = -10 mA
I_IN = 3 mA (see schematic)
V_I-O = 500 Vdc
f = 1 MHz, V_I-O = 0 Vdc
f = 1 MHz; V_IN = 0 V,
Pins 2 & 3, Pins 1 & 4 Open
Output Rise Time (10-90%)
t_r
10
s
Output Fall Time (90-10%)
t_f
0.5
s
Fig. Note
1
9
7
7
Notes:
1. Maximum operating frequency is defined when output waveform
(Pin 6) attains only 90% of V_CC with R_L = 1.8 k, C_L = 15 pF using a 5
V square wave input signal.
2. Measured at a point 1.6 mm below seating plane.
3. Current into/out of any single lead.
4. Surge input current duration is 3 ms at 120 Hz pulse repetition rate.
Transient input current duration is 10 s at 120 Hz pulse repetition
rate. Note that maximum input power, P_IN, must be observed.
5. Derate linearly above 100° C free-air temperature at a rate of 4.26
mW/°C. Maximum input power dissipation of 195 mW allows an
input IC junction temperature of 150°C at an ambient temperature
of T_A = 125° C with a typical thermal resistance from junction to
ambient of θ_JAi = 235°C/W. The typical thermal resistance from
junction to case is equal to 170°C/W. Excessive P_IN and T_J may result
in device degradation.
6. The 1.8 k load represents 1 TTL unit load of 1.6 mA and the 4.7 k
pull-up resistor.
7. Logic low output level at Pin 6 occurs under the conditions of V_IN
≥ V_TH+ as well as the range of V_IN > V_TH – once V_IN has exceeded V_TH+.
Logic high output level at Pin 6 occurs under the conditions of V_IN
≤ V_TH- as well as the range of V_IN < V_TH+ once V_IN has decreased
below V_TH-.
8. The AC voltage is instantaneous voltage.
9. Device considered a two terminal device: Pins 1, 2, 3, 4 connected
together, Pins 5, 6, 7 8 connected together.
10. This is a momentary withstand test, not an operating condition.
11. The t_PHL propagation delay is measured from the 2.5 V level of the
leading edge of a 5.0 V input pulse (1 s rise time) to the 1.5 V level
on the leading edge of the output pulse (see Figure 7).
12. The t_PLH propagation delay is measured from the 2.5 V level of the
trailing edge of a 5.0 V input pulse (1 μs fall time) to the 1.5 V level on
the trailing edge of the output pulse (see Figure 7).
13. Common mode transient immunity in Logic High level is the
maximum tolerable dV_CM/dt of the common mode voltage, V_CM,
to ensure that the output will remain in a Logic High state (i.e., V_O
> 2.0 V). Common mode transient immunity in Logic Low level is
the maximum tolerable dV_CM/dt of the common mode voltage, V_CM,
to ensure that the output will remain in a Logic Low state (i.e., V_O
< 0.8 V). See Figure 8.
14. In applications where dV_CM/dt may exceed 50,000 V/s (such
as static discharge), a series resistor, R_CC, should be included to
protect the detector IC from destructively high surge currents. The
recommended value for R_CC is 240  per volt of allowable drop in
V_CC (between Pin 8 and V_CC) with a minimum value of 240 .
15. D₁ and D₂ are Schottky diodes; D₃ and D₄ are zener diodes.
16. Standardpartsreceive100%testingat25°C(Subgroups1and9).SMD,
Class H and Class K parts receive 100% testing at 25, 125, and -55° C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively.)
17. Parameters shall be tested as part of device initial characterization
and after process changes. Parameters shall be guaranteed to the
limits specified for all lots not specifically tested.
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