AMMC-6232_15 Datasheet, PDF (7/8 Pages) AVAGO TECHNOLOGIES LIMITED – 14 LAMPS LED BULB

AMMC-6232 Application and Usage
To V_DD DC supply
0.1 uF Capacitor
RF INPUT
V_D1
V_D2
AMMC-6232
RF OUTPUT
To V_Gate DC supply
Figure 19. Gate Bias Combined Together
0.1 uF Capacitor
To V_DD DC supply
RF INPUT
V_D1
V_D2
AMMC-6232
RF OUTPUT
Gold Plated Shim (Optional)
To V_G1 DC supply
Figure 20. Separated Gate Bias
To V_G2 DC supply
Biasing and Operation
The AMMC-6232 is normally biased with a positive drain
supply connected to the VD1 and VD2 pads through
bypass capacitor as shown in Figures 15 and 16. The
recommended drain voltage and gate voltage for general
usage is 4V and -0.95V respectively. With Vdd=4V, Vg=-
0.95V, the corresponding drain current is approximately
135mA. It is important to have at least 0.1upF bypass
capacitor and the capacitor should be placed as close
to the component as possible. Aspects of the amplifier
performance may be improved over a narrower bandwidth
by application of additional conjugate, linearity, or low
noise (Topt) matching.
After adjusting the gate bias to obtain 135mA at Vdd
= 4V, the AMMC-6232 can be safely biased at Vdd=
3V or 5V (while fixing the gate bias) as desired. At 4V,
the performance is an optimal compromise between
power consumption, gain and power/linearity. It is both
applicable to be used as a low noise block or driver. At 3V,
the amplifier is ideal as a front end low noise block where
linearity is not highly required. At 5V, the amplifier can
provide ~ 2dB more output power for LO or transmitter
driver applications where high output power and linearity
are often required.
The two gate voltages can be combined as shown in
Figure 15 or separated as in Figure 16. Combining the two
gate voltages simplifies the usage whereas separating
them provides flexibility to overall biasing scheme.
In both cases, bonding wires at the input and output in
the range of 0.15nH would likely improve the overall Noise
Figure and input, output match at most frequencies.
No ground wires are needed because ground connection
is made with plated through-holes to the backside of the
substrate.
Figure 21. Simplified High Linearity LNA Schematic