AMMP-6120 Datasheet, PDF (6/7 Pages) AVAGO TECHNOLOGIES LIMITED – 8-24 GHz x2 Frequency Multiplier 5x5mm Surface Mount Package

20
18 ^Fout=26GHz
16 ^{Vd=4.5V, Vg=-1.2V}
14
12
10
8
6
4
2
0
-11 -9 -7 -5 -3 -1
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
1 3 5 7 9 11
Input Power [1H] (dBm)
Figure 19 . 2H Output Power Vs Input Power @ Fout=26GHz
5
Fout=26GHz
10
15
20
25
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
30
Vg=-1.4V, Vd=5.0V
35
-11 -9 -7 -5 -3 -1 1 3 5 7 9 11
Input Power [1H] (dBm)
Figure 20 . Fundamental Supp. Vs Input Power @ Fout=26GHz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
1.E+02
1.E+03
1.E+04
Fout=15.6GHz
1.E+05 1.E+06
1.E+07
M/N
Active
@ fo
Balun
F1
S
Filter
Amp
@ 2fo
F2
O set Frequency [Hz]
Figure 21. SSB Phase Noise of frequency doubler
(Pin=+2dBm, fout=15.6GHz)
Figure 22. Top Level Schematic of Frequency doubler
Biasing and Operation
The frequency doubler MMIC consists of a balun. The
outputs of this balun feed the gates of balanced FETs and
the drains are connected to form the single-ended output.
This results in fundamental frequency & odd harmon-
ics cancellation. The even harmonic drain currents are in
phase and thus add in phase. The input matching network
(M/N) is designed to provide good match at fundamental
frequencies and produces high impedance mismatch to
higher harmonics.
The AMMP-6120 is biased with a single positive drain
supply Vdd and a single negative gate supply using sepa-
rate bypass capacitors. It is normally biased with the drain
supply connected to Vd and the gate supply connected to
Vg. For most applications it is recommended to use a Vg
=-1.2V to -1.4V and Vd=4.5V to 5.0V.
The RF input and output ports are AC coupled thus no DC
voltage is present at either port. The ground connection is
made via the package base.”
The AMMP-6120 performance changes with Drain Voltage
(Vd) and Gate bias (Vg) as shown in the previous graphs.
Improvements in output power or fundamental suppres-
sion performance are possible by optimizing the Vg from
-1.2V to -1.4V and/or Vd from 4.5 to 5.0V.
A simplified schematic of the frequency multiplier is
shown in figure 22. The active balun circuit and the output
amplifier of the circuit are self biased. The Vg negative bias
(below pinch off ) is only applied to FETs ‘F1’ and ‘F2’. FETs
‘F1’ and ‘F2’ have no significant contribution to total drain
current therefore Vg cannot be used to set drain current.
It should only be used to optimize the output power
and fundamental & higher harmonics suppression of the
doubler.
Refer to the Absolute Maximum Ratings table for allowed
DC and thermal conditions.
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