AFCT-57V6NSZ Datasheet, PDF (6/22 Pages) AVAGO TECHNOLOGIES LIMITED – Small Form Factor Pluggable (SFP) LC Optical Transceiver for 1.25GBd Ethernet at Extended Link Lengths (Up to 40km)

Pin Description
A brief description of all of the electrical connector pins follows. The connector has staged contacts, so that hot-plug-
ging can be performed. See Table 10.
Table 10. Pinout
Pin No.
1
2
3
4
5
6
7
8
9
10
Sequence
1
3
3
3
3
3
3
3
1
1
Description
VeeT
TX_FAULT
TX_DISABLE
MOD_DEF[2]
MOD_DEF[1]
MOD_DEF[0]
RATE_SELECT
RX_LOS
VeeR
VeeR
Pin No
11
12
13
14
15
16
17
18
19
20
Sequence
1
3
3
1
2
2
1
3
3
1
Description
VeeR
RD-
RD+
VeeR
VccR
VccT
VeeT
TD+
TD-
VeeT
Hot-Plugging Sequence
The ground, VCC and other pins designated as the se-
quence (1) pins engage first during hot-plugging. The
sequence (2) pins connect second during hot-plugging
followed by the sequence (3) pins. Conversely, when
the module is unplugged from the host system, the se-
quence (3) pins disengages before the sequence (2) pins
disengages and then followed by the sequence (1) pins.
Inserting or removing the AFCT-57V6NSZ will disrupt
data transmission. This disruption occurs when the
downstream receiver (e.g. deserializer phase-lock-loop)
resynchronizes to a different bitstream signal. When this
occurs, the downstream system will recognize the asso-
ciated error (e.g. comma detect, loss-of-light, disparity,
CRC, and frame errors).
It is the responsibility of the system integrator to assure
that no thermal, energy, or voltage hazard exists during
the hot-plug-unplug sequence. It is also the responsibility
of the system integrator and end-user to minimize static
electricity and the probability of ESD events by careful
design.
20 ^VeeT
19 ^TD-
18 ^TD+
17 ^VeeT
16 ^VccT
15 ^VccR
14 ^VeeR
13 ^RD+
12 ^RD-
11 ^VeeR
1 VeeT
2 TX_FAULT
3 TX_DISABLE
4 MOD_DEF[2]
5 MOD_DEF[1]
6 MOD_DEF[0]
7 RATE_SELECT
8 RX_LOS
9 ^VeeR
10 VeeR
Top of Board
Bottom of Board
(as view through top of board)
Figure 3. SFP Transceiver Electrical Pad Layout