AFBR-5710LZ_15 Datasheet, PDF (4/20 Pages) AVAGO TECHNOLOGIES LIMITED – Transceivers with Optional DMI for Gigabit Ethernet

Functional I/O
The AFBR-571xZ accepts industry standard differential
signals such as LVPECL and CML within the scope of the
SFP MSA. To simplify board requirements, transmitter bias
resistors and ac coupling capacitors are incorporated, per
SFF-8074i, and hence are not required on the host board.
The module is AC-coupled and internally terminated.
Figure 3 illustrates a recommended interface circuit to
link the AFBR-571xZ to the supporting Physical Layer
integrated circuits.
Timing diagrams for the MSA compliant control signals
implemented in this module are depicted in Figure 6.
The AFBR-571xZ interfaces with the host circuit board
through twenty I/O pins (SFP electrical connector)
identified by function in Table 2. The AFBR-571xZ high
speed transmit and receive interfaces require SFP MSA
compliant signal lines on the host board. The Tx_Disable,
Tx_Fault, and Rx_LOS lines require TTL lines on the host
board (per SFF-8074i) if used. If an application chooses
not to take advantage of the functionality of these pins,
care must be taken to ground Tx_Disable (for normal
operation).
Digital Diagnostic Interface and Serial Identification
(EEPROM)
The entire AFBR-571xZ family complies with the SFF-
8074i SFP specification. The AFBR-5715Z family further
complies with SFF-8472, the SFP specification for Digital
Diagnostic Monitoring Interface. Both specifications can
be found at http://www.sffcommittee.org.
The AFBR-571xZ features an EEPROM for Serial ID, which
contains the product data stored for retrieval by host
equipment. This data is accessed via the 2-wire serial
EEPROM protocol of the ATMEL AT24C01A or similar, in
compliance with the industry standard SFP Multi-Source
Agreement. The base EEPROM memory, bytes 0-255 at
memory address 0xA0, is organized in compliance with
SFF-8074i. Contents of this serial ID memory are shown
in Table 10.
The I2C accessible memory page address 0xB0 is used
internally by SFP for the test and diagnostic purposes
and it is reserved.
VCCT,R
1 µH
10 µF 0.1 µF
1 µH
*RES
0.1
µF
GP04
TX_FAULT
VREFR
TBC
EWRAP
MAC
ASIC
RBC
RX_RATE
RX_LOS
SO1+
TX[0:9]
SO1–
SYNC
LOOP
AVAGO
HDMP-1687
RX[0:9]
SYN1
SI1+
RC1(0:1)
RCM0
RFCT
SI1–
VCCT,R
R
*RES
*RES
50 Ω
50 Ω
10 0.1
µF µF
50 Ω
50 Ω
*RES *RES
GPIO(X)
GPIO(X)
GP14
REFCLK
125 MHz
Figure 3. Typical application configuration.
NOTE: * 4.7 k Ω < RES < 10 kΩ
HOUSING
GROUND
VCCT
*RES
AVAGO
AFBR-571xZ
TX_DISABLE
TX_FAULT
TD+
C
C
R
TD–
VEET
LASER DRIVER
& EYE SAFETY
CIRCUITRY
VCCR
RD+
C
C _RD–
REF_RATE
AMPLIFICATION
&
QUANTIZATION
RX_LOS
MOD_DEF2
MOD_DEF1
MOD_DEF0
VEER
EEPROM
4