HDSP-0781_08 Datasheet, PDF (3/8 Pages) AVAGO TECHNOLOGIES LIMITED – Glass/Ceramic Numeric and Hexadecimal Displays for Industrial Applications

DATA INPUT
(LOW LEVEL DATA)
t_SETUP t_HOLD
1.5 V
1.5 V
DATA INPUT
(HIGH LEVEL DATA)
ENABLE
INPUT
1.5 V
1.5 V
10%
1.5 V
t_TLH
1.5 V ^90%
t_W
Figure 1. Timing diagram.
V_CC 7
ENABLE 5
LOGIC 8
1
INPUT 2
3
DP⁽²⁾ 4
X1
X2
X4
LATCH
X8 MEMORY
DP
BLANKING⁽³⁾ 4
CONTROL
GROUND 6
DP
LED
MATRIX
DRIVER
Figure 2. Block diagram.
MATRIX
DECODER
LED
MATRIX
BCD DATA^[1]
X₈
X₄
X₂
L
L
L
TRUTH TABLE
NUMERIC
X₁
L
HEXADECIMAL
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
(BLANK)
H
H
L
L
(BLANK)
H
H
L
H
••••
H
H
H
L
(BLANK)
H
H
H
DECIMAL PT.^[2]
ENABLE^[1]
BLANKING^[3]
H
(BLANK)
ON
OFF
LOAD DATA
LATCH DATA
DISPLAY–ON
DISPLAY–OFF
V_DP = L
V_DP = H
V_E = L
V_E = H
V_B = L
V_B = H
NOTES:
1. H = LOGIC HIGH; L = LOGIC LOW. WITH THE ENABLE INPUT AT
LOGIC HIGH, CHANGES IN BCD INPUT LOGIC LEVELS HAVE NO
EFFECT UPON DISPLAY MEMORY, DISPLAYED CHARACTER, OR DP.
2. THE DECIMAL POINT INPUT, DP, PERTAINS ONLY TO THE
NUMERIC DISPLAYS.
3. THE BLANKING CONTROL INPUT, B, PERTAINS ONLY TO THE
HEXADECIMAL DISPLAYS. BLANKING INPUT HAS NO EFFECT
UPON DISPLAY MEMORY.