AFBR-811FX3Z Datasheet, PDF (28/54 Pages) AVAGO TECHNOLOGIES LIMITED – 10 Gbps/Channel, 300m link Twelve Channel, Parallel Fiber Optics Modules

The following characteristics are defined over the Recommended Operating Conditions, unless otherwise noted. Typical
values are for T_c = 40 °C, V_cc33 = 3.435 V and V_cc25 = 2.625 V.
Parameter
Symbol
Min
Typ
Max
Units Reference
LVTTL Input Voltage High Threshold
Vihttl
2
V
1
LVTTL Input Voltage Low Threshold
Vilttl
0.8
V
1
LVTTL Output Pull-up Current
Ioputtl
80
250
mA
Pull-up to 3.3 V
LVTTL Output Pull-down Current
Ioputtl
80
250
mA
Pull-down to 0.0 V
Address Assert Time
6.6
100
ms
2
Interrupt Assert Time
Interrupt Pulse Width
Interrupt De-assert Time
Reset Assert Time
Reset De-assert Time
Initialization Time TWS Interfaces
t_{INTL ON}
t_{INTL PW}
5
t_{INTL OFF}
t_{RSTL ON}
t_{RSTL OFF}
180
300
ms
3
28
50
ms
4
20
500
ms
5
0.2
100
ms
6
350
2000
ms
7
2000
ms
Data Ready Time
Tx Fault Assert Time
Flag Assert Time
Mask Assert Time
Mask Deassert Time
Select Change Time
TWS Data In Set Up Time
TWS Data In Hold Time
TWS Clock Low to Data Out Valid
TWS Data Out Hold Time
TWS Data Output Rise Time
TWS Data Output Fall Time
TWS Interface Timing
t_data
2000
ms
8
t_Txfault,ON
200
ms
9
t_flag,ON
200
ms
10
t_mask,OFF
100
ms
11
t_mask,ON
100
ms
12
t_ratesel
100
ms
13
t_SU:SDA
0.10
ms
14
t_HD:SDA
0
ms
15
t_AA
0.10
0.90
ms
16
t_DH
100
ns
17
t_{r SDA}
t_{f SDA}
0.30
ms
0.30
ms
Measured between
0.8 V and 2.0 V
See Atmel Two-Wire Serial EEPROM, e.g., AT24C01A. Note difference in Write Cycle Time
TWS Write Cycle Time
t_WC
100
ms
(up to 2 sequential bytes)
Serial Interface Clock Holdoff –
“Clock Stretching”
T_clock_hold
500
ms
18
Endurance (Write cycles)
50,000
cycles 19
Notes:
1. 3.3 V LVTTL compatible control inputs. This includes ADR[2:0] pins.
2. Is the module response time from a change in module address, Adr[2:0], to response to TWS communication using the new address.
3. This is the module response time from occurrence of interrupt generating event to IntL assertion, V_out:IntL = Vol.
4. Pulse or static level can be selected for IntL. Static mode is default. See Memory Map.
5. This is the module response time from clear on read operation, measured from falling SCL edge after stop bit of read transaction, until Vout:IntL
= Voh where IntL is in static mode.
6. Assertion of ResetL activates a complete module reset, i.e. module returns to factory default and non-volatile control settings. While ResetL is Low,
TX and RX outputs are disabled and the module does not respond to the TWS interface.
7. This is the response time from ResetL de-assertion to resumption of operation.
8. Time from power on to Data Not Ready (Byte 2, bit 0) deasserted and Int_L asserted.
9. Time from Tx Fault state to Tx Fault bit set (value = 1b) and Int_L asserted
10. Time from occurrence of condition triggering flag to associated flag bit set (value = 1b) and Int_L asserted
11. Time from mask bit set (value = 1b) until associated Int_L assertion is inhibited.
12. Time from mask bit cleared (value = 0b) until associated Int_L operation resumes.
13. Time from change of state of Application or Rate Select bit until transmitter or receiver bandwidth is in conformance with appropriate specification
14. Data In Set Up Time is measured from Vil(max)SDA or Vih(min)SDA to Vil(max)SCL.
15. Data In Hold Time is measured from Vil(max)SCL to Vil(max)SDA or Vih(min)SDA.
16. Clock Low to Data Out Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.
17. Data Out Hold Time is measured from Vil(max)SCL to Vol(max)SDA or Voh(min)SDA.
18. Maximum time the modules may hold the SCL line low before continuing with a read or write operation.
19. 50 K write cycles at 70 °C. Applies to non-volatile control registers in memory map.
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