HFBR-2404Z Datasheet, PDF (21/24 Pages) AVAGO TECHNOLOGIES LIMITED – Low-Cost, 820 nm Miniature Link Fiber Optic Components with ST, SMA, SC and FC Ports

HFBR-24x6Z Low-Cost 125 MHz Receiver
Description
The HFBR-24x6Z fiber optic receiver is designed to oper-
ate with the Avago Technologies HFBR-14xxZ fiber optic
transmitters and 50/ 125 µm, 62.5/125 µm, 100/140 µm
and 200 µm Plastic-Clad Silica (PCS) fiber optic cable.
Consistent coupling into the receiver is assured by the
lensed optical system (Figure 1). Response does not vary
with fiber size for core diameters of 100 µm or less.
The receiver output is an analog signal which allows
follow-on circuitry to be optimized for a variety of dis-
tance/data rate requirements. Low-cost external compo-
nents can be used to convert the analog output to logic
compatible signal levels for various data formats and
data rates up to 175 MBd. This distance/data rate trade-
off results in increased optical power budget at lower
data rates which can be used for additional distance or
splices.
The HFBR-24x6Z receiver contains a PIN photodiode and
low noise transimpedance preamplifier integrated circuit.
The HFBR-24x6Z receives an optical signal and converts
it to an analog voltage. The output is a buffered emitter
follower. Because the signal amplitude from the HFBR-
24x6Z receiver is much larger than from a simple PIN
photodiode, it is less susceptible to EMI, especially at high
signaling rates. For very noisy environments, the conduc-
tive or metal port option is recommended. A receiver
dynamic range of 23 dB over temperature is achievable,
assuming a Bit Error Rate (BER) of 10^-9.
The frequency response is typically dc to 125 MHz. Al-
though the HFBR-24x6Z is an analog receiver, it is com-
patible with digital systems.
The recommended ac coupled receiver circuit is shown
in Figure 14. A10 Ω resistor must be connected between
pin 6 and the power supply, and a 100 nF ceramic bypass
capacitor must be connected between the power sup-
ply and ground. In addition, pin 6 should be filtered to
protect the receiver from noisy host systems. Refer to AN
1065 for details.
BIAS & FILTER
CIRCUITS
5.0
mA
Figure 13. Simplified Schematic Diagram.
6
VCC
POSITIVE
SUPPLY
300 pF
2
VOUT
ANALOG
SIGNAL
3, 7
VEE
NEGATIVE
SUPPLY
Housed Product
6
V_cc
2 _{ANALOG SIGNAL}
3 & 7 _VEE
45
36
27
18
BOTTOM VIEW
PIN 1 INDICATOR
PIN FUNCTION ^NOTES:
1¹ NC
1. PINS 1, 4, 5 AND 8 ARE ISOLATED
2 SIGNAL
FROM THE INTERNAL CIRCUITRY,
3² V_EE
4¹ NC
BUT ARE CONNECTED TO EACH OTHER.
2. PINS 3 AND 7 ARE ELECTRICALLY
5¹ NC
CONNECTED TO THE HEADER.
6
V_CC
7² V_EE
8¹ NC
CAUTION: The small junction sizes inherent to the design of these components increase the components’ susceptibility to damage
from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of these compo-
nents to prevent damage and/or degradation which may be induced by ESD.
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