AFBR-79EIPZ Datasheet, PDF (17/20 Pages) AVAGO TECHNOLOGIES LIMITED – 4 x 10 Gb Ethernet and InfiniBand Applications

Control Interface
The control interface combines dedicated signal lines for
ModSelL, LPMode, ResetL, ModPrsL, IntL with two-wire
serial (TWS), interface clock (SCL) and data (SDA), signals
to provide users rich functionality over an efficient and
easily used interface. The TWS interface is implemented
as a slave device and compatible with industry standard
two-wire serial protocol. It is scaled for 3.3 volt LVTTL.
Outputs are high-z in the high state to support busing of
these signals. Signal and timing characteristics are further
defined in the Control I/O Characteristics section. For
more details, see QSFP+ SFF-8436.
ModSelL
The ModSelL is an input signal. When held low by the
host, the module responds to 2-wire serial communica-
tion commands. The ModSelL allows the use of multiple
QSFP+ modules on a single 2-wire interface bus. When
the ModSelL is “High”, the module will not respond to or
acknowledge any 2-wire interface communication from
the host. ModSelL signal input node is biased to the “High”
state in the module. In order to avoid conflicts, the host
system shall not attempt 2-wire interface communica-
tions within the ModSelL de-assert time after any QSFP+
module is deselected. Similarly, the host must wait at least
for the period of the ModSelL assert time before communi-
cating with the newly selected module. The assertion and
de-assertion periods of different modules may overlap as
long as the above timing requirements are met.
ResetL
The ResetL signal is pulled to Vcc in the QSFP+ module.
A low level on the ResetL signal for longer than the
minimum pulse length (t_Reset_init) initiates a complete
module reset, returning all user module settings to their
default state. Module Reset Assert Time (t_init) starts on
the rising edge after the low level on the ResetL pin is
released. During the execution of a reset (t_init) the host
shall disregard all status bits until the module indicates a
completion of the reset interrupt. The module indicates
this by posting an IntL signal with the Data_Not_Ready bit
negated. Note that on power up (including hot insertion)
the module will post this completion of reset interrupt
without requiring a reset.
LPMode
Low power mode. When held high by host, the module
is held at low power mode. When held low by host, the
module operates in the normal mode. For class 1 power
level modules (1.5W), low power mode has no effect.
ModPrsL
ModPrsL is pulled up to Vcc_Host on the host board and
grounded in the module. The ModPrsL is asserted “Low”
when module is inserted into the host connector, and
deasserted “High” when the module is physically absent
from the host connector.
IntL
IntL is an output signal. When “Low”, it indicates a possible
module operational fault or a status critical to the host
system. The host identifies the source of the interrupt
using the 2-wire serial interface. The IntL signal is an
open collector output and must be pulled to host supply
voltage on the host board. A corresponding soft status
IntL signal is also available in the transceiver memory
page 0 address 2 bit 1.
Soft Status and Control
A number of soft status signals and controls are available
in the AFBR-79EIPZ transceiver memory and accessible
through the TWS interface. Some soft status signals
include receiver LOS, optional transmitter LOS, transmitter
fault and diagnostic monitor alarms and warnings. Some
soft controls include transmitter disable (Tx_Dis), receiver
output disable (Rx_Dis), transmitter squelch disable (Tx_
SqDis), receiver squelch disable (Rx_SqDis), and masking
of status signal in triggering IntL. All soft status signals
and controls are per channel basis. All soft control entries
are volatile.
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