AFBR-775BZ Datasheet, PDF (16/48 Pages) AVAGO TECHNOLOGIES LIMITED – Pluggable, Parallel-Fiber-Optics

Receiver Module Contact Assignment and Signal Description
O ptical Connector Side
Adr2 GND GND GND GND GND GND GND GND IntL K
Adr1 GND Dout1p GND Dout4p GND Dout8n GND Dout11n GND J
Adr0 GND Dout1n GND Dout4n GND Dout8p GND Dout11p GND H
GND Dout0p GND Dout3p GND Dout6n GND Dout10n GND SDA G
GND Dout0n GND Dout3n GND Dout6p GND Dout10p GND SCL F
ResetL GND Dout2p GND Dout5n GND Dout7n GND Dout9p GND E
DNC GND Dout2n GND Dout5p GND Dout7p GND Dout9n GND D
DNC DNC GND DNC GND DNC GND DNC GND DNC C
GND GND GND DNC DNC DNC DNC GND GND GND B
Vcc25 Vcc33 Vcc33 DNC DNC DNC DNC Vcc33 Vcc33 Vcc25 A
10 9
8
7
6
5
4
3
2
1
Figure 10. Host Board Pattern for Receiver Connector – Top View
PIN name
Adr[2:0]
Dout[11:0]p
Dout[11:0]n
DNC
GND
IntL
ResetL
SDA
SCL
Vcc25
Vcc33
Case
Common
Functional descriptions
TWS Module Bus Address bits: Address has the form 0101hjkx where Adr2, Adr1 & Adr0
correspond to h, j & k respectively and x corresponds to the R/W command.
Receiver Data Non-inverting Output for channels 11 through 0
Receiver Data Inverting Output for channels 11 through 0
Reserved – Do Not Connect to any electrical potential on Host PCB
Signal Common: All module voltages are referenced to this potential unless otherwise stated.
Connect these pins directly to the host board signal ground plane.
Interrupt signal to Host, Asserted Low: An interrupt is generated in response to loss of input
signal or assertion of any monitor Flag. It may be programmed through the TWS interface to
generate either a pulse or static level with pulse mode as default. This output presents a High-Z
condition when IntL is de-asserted and requires a pull-up on the Host board. Pull-up to the
Host 3.3 V supply is recommended.
Reset signal to module, Asserted Low: When asserted the data outputs, Dout[11:0]p/n are
squelched, TWS interface commands are inhibited, and the module returns to default and
non-volatile settings. An internal pullup biases the input High if the input is open.
TWS interface data signal: Pull-up with a 2.0 kΩ to 8.0 kΩ resistor to the Host 3.3 V supply is
recommended.
TWS interface clock signal: Pull-up with a 2.0 kΩ to 8.0 kΩ resistor to the Host 3.3 V supply is
recommended.
2.5V Power supply, External common connection of pins required – not common internally
3.3 V Power supply, External common connection of pins required – not common internally
Not accessible in connector. Case common incorporates exposed conductive surfaces includ-
ing threaded bosses and is electrically isolated from signal common, i.e. GND. Connect as
appropriate for EMI shield integrity. See EMI clip and bezel cutout recommendation.
I/O Type
I 3.3V LVTTL
O CML
O CML
O 3.3V LVTTL,
high-Z or
driven to 0
level
I 3.3V LVTTL
I/O 3.3V LVTTL/
Open-Drain
I 3.3V LVTTL
P
P
16