MGA-43828_15 Datasheet, PDF (12/16 Pages) AVAGO TECHNOLOGIES LIMITED – 925–960 MHz Linear Power Amplifier Module

Application Schematic
Vdd2
Vdd3
C7
Idq2
C10
Idq3
C11
C8
C9
C13
1
RFin C1
Top View
RFout
C2
C20 C22
Vc2 Vc3
C24
I_Vddbias
C25
C26
C28
Vdet
C29
Vddbias
Figure 26. Application schematic in demonstration board
Notes
1. All capacitors on supply lines are bypass capacitors
2. C1 / C2 are RF coupling capacitors.
3. For Vdd=VddBias=5V, Idq2 = 110 mA, Idq3 = 235 mA, I_VddBias = 14 mA. Idq 2/3 are adjusted by voltages to CMOS-compatible control pins Vc
2/3 respectively. These typical bias currents were obtained with Vc 2/3 voltages in Fig 2 below. Adjustment of these currents enable optimum bias
conditions to be achieved for best linearity and efficiency for a given modulation type.
MGA-43828 typical Ic2, Ic3 vs Vc unless otherwise stated
135
Ic2
Ic3
125
135
Ic2
Ic3
125
115
115
105
105
95
95
85
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vc,V
Figure 27. Ic Versus Vc at Vdd=VddBias=5.0V
85
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vc,V
Figure 28. Ic Versus Vc at Vdd=VddBias=5.5V
12