APDS-9300-020 Datasheet, PDF (12/21 Pages) AVAGO TECHNOLOGIES LIMITED – Miniature Ambient Light Photo Sensor with Digital (I2C) Output

Interrupt Threshold Register (2h - 5h)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison func-
tion for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low threshold specified,
an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses above the high threshold speci-
fied, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW and THRESHLOWHIGH provide the low byte
and high byte, respectively, of the lower interrupt threshold. Registers THRESHHIGHLOW and THRESHHIGHHIGH provide
the low and high bytes, respectively, of the upper interrupt threshold. The high and low bytes from each set of registers
are combined to form a 16–bit threshold value. The interrupt threshold registers default to 00h on power up.
Table 7. Interrupt Threshold Register
Register
THRESHLOWLOW
THRESHLOWHIGH
THRESHHIGHLOW
THRESHHIGHHIGH
Address
Bits
2h
7:0
3h
7:0
4h
7:0
5h
7:0
Description
ADC channel 0 lower byte of the low threshold
ADC channel 0 upper byte of the low threshold
ADC channel 0 lower byte of the high threshold
ADC channel 0 upper byte of the high threshold
NOTE: Since two 8–bit values are combined for a single 16–bit value for each of the high and low interrupt thresholds, the Send Byte protocol
should not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired. The Write
Word protocol should be used to write byte–paired registers. For example, the THRESHLOWLOW and THRESHLOWHIGH registers (as well as the
THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16–bit ADC value in a single transaction.
Interrupt Control Register (6h)
The INTERRUPT register controls the extensive interrupt capabilities of the APDS-9300. The APDS-9300 permits tradi-
tional level–style interrupts. The interrupt persist bit field (PERSIST) provides control over when interrupts occur. A value
of 0 causes an interrupt to occur after every integration cycle regardless of the threshold settings. A value of 1 results
in an interrupt after one integration time period outside the threshold window. A value of N (where N is 2 through15)
results in an interrupt only if the value remains outside the threshold window for N consecutive integration cycles. For
example, if N is equal to 10 and the integration time is 402 ms, then the total time is approximately 4 seconds.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value outside of
the programmed threshold window. The interrupt is active–low and remains asserted until cleared by writing the COM-
MAND register with the CLEAR bit set.
NOTE: Interrupts are based on the value of Channel 0 only.
Table 8. Interrupt Control Register
7
6
5
4
3
6h
Resv
Resv
INTR
2
1
PERSIST
0
INTERRUPT
Reset Value:
0
0
0
0
0
0
0
0
Field
Bits
Resv
7:6
INTR
5:4
PERSIST
3:0
Description
Reserved.Write as 0.
INTR Control Select.This field determines mode of interrupt logic according to Table 9,
below.
Interrupt persistence.Controls rate of interrupts to the host processor as shown in Table 10,
below.
12