AFBR-53D5Z_15 Datasheet, PDF (10/15 Pages) AVAGO TECHNOLOGIES LIMITED – 850 nm VCSEL Fibre Optic Transceivers for Gigabit Ethernet

LASER
DRIVER
CIRCUIT
PECL
INPUT
C5
0.1 µF
V _EET ⁹
8
TD+
TD- 7
5 Vdc
R3 R2
68 68
C9 0.01 µF
C10 0.01 µF
R4 R1
191 191
AFBR-53D5Z
FIBER-OPTIC
TRANSCEIVER
V _CCT ⁶ _C2
L2
1 µH
0.1 µF
V _CCR ⁵ _C1
L1
+C8* 1 µH
0.1
10 µF*
µF
3.3 Vdc
+
GND
50 Ω
50 Ω
V _CC2 V _EE2
TD+
OUTPUT
DRIVER
TD-
R13 R12
150 150
CLOCK
SYNTHESIS
CIRCUIT
PARALLEL
TO SERIAL
CIRCUIT
5 Vdc
C3
+ C4
0.1
10
µF
µF
HDMP-1636A/-1646A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
TRANSCEIVER)
SIGNAL
DETECT
CIRCUIT
SD 4
R9
TO SIGNAL DETECT (SD)
INPUT AT UPPER-LEVEL-IC
PRE-
AMPLIFIER
RD- 3
POST-
AMPLIFIER
RD+ 2
V _EER ¹
270
R11 R10
270 270
C12 0.01 µF
C11 0.01 µF
50 Ω
R14
100
50 Ω
RD-
INPUT
BUFFER
RD+
CLOCK
RECOVERY
CIRCUIT
SERIAL TO
PARALLEL
CIRCUIT
SEE HDMP-1636A/-1646A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
NOTES:
*C8 IS AN OPTIONAL BYPASS CAPACITOR FOR ADDITIONAL LOW-FREQUENCY NOISE FILTERING.
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50 Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50 Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
Figure 3. Recommended Gigabit/sec Ethernet AFBR-53D5Z Fiber-Optic Transceiver and HDMP-1636A/1646A SERDES Integrated Circuit Transceiver Interface
and Power Supply Filter Circuits.
20.32
0.800
(2X)
∅
1.9 ± 0.1
0.075 ± 0.004
-A-
∅0.000 M A
20.32
0.800
(9X)∅
0.8 ± 0.1
0.032 ± 0.004
∅0.000 M A
(8X)
2.54
0.100
TOP VIEW
Figure 4. Recommended Board Layout Hole Pattern.
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