PEX8750 Datasheet, PDF (1/5 Pages) AVAGO TECHNOLOGIES LIMITED – PCI Express Gen3 Switch

PEX8750, PCI Express Gen3 Switch, 48 Lanes, 12 Ports
Highlights
 PEX8750 General Features
o 48-lane, 12-port PCIe Gen3 switch
- Integrated 8.0 GT/s SerDes
o 27 x 27mm², 676-ball FCBGA package
o Typical Power: 10.3 Watts
 PEX8750 Key Features
o Standards Compliant
- PCI Express Base Specification, r3.0
(compatible w/ PCIe r1.0a/1.1 & 2.0)
- PCI Power Management Spec, r1.2
- Microsoft Windows Logo Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
o High Performance
 performancePAK
 Multicast
 Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric
- Full line rate on all ports
- Cut-Thru with 150ns max packet latency
- 2KB Max Payload Size
o Multi-Host & Fail-Over Support
- 2 Configurable Non-Transparent ports
- Failover with Non-Transparent port
- Up to 3 upstream/Host ports with 1+1 or
N+1 failover to other upstream ports
o Quality of Service (QoS)
- Traffic Class Queuing
- Eight traffic classes per port
- Weighted round-robin source
port arbitration
o Reliability, Availability, Serviceability
 visionPAK
 Per Port Performance Monitoring
 SerDes Eye Capture
 PCIe Packet Generator
 Error Injection and Loopback
- 4 Hot-Plug port with native HP Signals
- All ports Hot-Plug capable thru I²C
- SSC Isolation on up to 12 ports
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- Advanced Error Reporting
- Port Status bits and GPIO available
- JTAG AC/DC boundary scan
The ExpressLane^TM PEX8750 device offers Multi-Host PCI Express
switching capability enabling users to connect multiple hosts to their
respective endpoints via scalable, high bandwidth, non-blocking
interconnection to a wide variety of applications including servers, storage
systems, and communications platforms. The PEX8750 is well suited for
fan-out, aggregation, and peer-to-peer applications.
Multi-Host Architecture
The PEX8750 employs an enhanced architecture, which allows users to
configure the device in legacy single-host mode or multi-host mode with up
to three host ports capable of 1+1 (one active & one backup) or N+1 (N
active & one backup) host failover. This powerful architectural enhancement
enables users to build PCIe based systems to support high-availability,
failover, redundant and clustered systems.
High Performance & Low Packet Latency
The PEX8750 architecture supports packet cut-thru with a maximum
latency of 150ns (x16 to x16). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
Data Integrity
The PEX8750 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
Flexible Configuration
The PEX8750’s 12 ports can be configured to
lane widths of x4, x8, or x16. Flexible buffer
allocation, along with the device's flexible
packet flow control, maximizes throughput
for applications where more traffic flows in
the downstream, rather than upstream,
direction. Any port can be designated as the
upstream port, which can be changed
dynamically. Figure 1 shows some of the
PEX8750’s common port configurations in
legacy Single-Host mode.
The PEX8750 can also be configured in Multi-Host mode where users can
choose up to four ports as host/upstream ports and assign a desired number of
downstream ports to each host. In Multi-Host mode, a virtual switch is
created for each host port and its associated downstream ports inside the
device. The traffic between the ports of a virtual switch is completely
isolated from the traffic in other virtual switches. Figure 2 illustrates some
configurations of the PEX8750 in Multi-Host mode where each ellipse
represents a virtual switch inside the device.
© PLX Technology, www.plxtech.com
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10Sep12; v1.0