PEX8747 Datasheet, PDF (1/4 Pages) AVAGO TECHNOLOGIES LIMITED – PCI Express Gen 3 Switch

PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports
Highlights
ƒ PEX 8747 General Features
o 48-lane, 5-port PCIe Gen 3 switch
- Integrated 8.0 GT/s SerDes
o 27 x 27mm², 676-pin FCBGA package
o Typical Power: 8.0 Watts
ƒ PEX 8747 Key Features
o Standards Compliant
- PCI Express Base Specification, r3.0
(compatible w/ PCIe r1.0a/1.1 & 2.0)
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
o High Performance
♦ performancePAK
9 Read Pacing (bandwidth throttling)
9 Multicast
9 Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 100ns max packet
latency (x16 to x16)
- 2KB Max Payload Size
o Flexible Configuration
- Ports configurable as x8 or x16
- Registers configurable with strapping
pins, EEPROM, I²C, or host software
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM
o Quality of Service (QoS)
- Eight traffic classes per port
- Weighted round-robin source
port arbitration
o Reliability, Availability, Serviceability
♦ visionPAK
9 Per Port Performance Monitoring
ƒ Per port payload & header counters
9 SerDes Eye Capture
9 PCIe Packet Generator
9 Error Injection and Loopback
- All ports hot plug capable thru I²C
(Hot Plug Controller on every port)
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
- Port Status bits and GPIO available
• Per port error diagnostics
- JTAG AC/DC boundary scan
The ExpressLane™ PEX 8747 device offers Multi-Host PCI Express
switching capability enabling users to connect a host to its respective
endpoints via scalable, high bandwidth, non-blocking interconnection
to a variety of graphics applications. The PEX 8747 is optimized to
support high-resolution graphics while supporting peer-to-peer traffic
and multicast for maximum performance.
High Performance & Low Packet Latency
The PEX 8747 architecture supports packet cut-thru with a maximum
latency of 100ns (x16 to x16). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
Data Integrity
The PEX 8747 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
Flexible Configuration
The PEX 8747’s 5 ports can be
configured to lane widths of x8 or
x16. Flexible buffer allocation,
along with the device's flexible
packet flow control, maximizes
throughput for applications where
more traffic flows in the
downstream, rather than
upstream, direction. Any port can
be designated as the upstream
port, which can be changed
dynamically. Figure 1 shows
some of the PEX 8747’s common
port configurations.
x16
x16
PEX 8747
x16 x16
PEX 8747
x16 x8 x8
x16
PEX 8747
x8 x8 x8 x8
Figure 1. Common Port Configurations
SerDes Power and Signal Management
The PEX 8747 provides low power capability that is fully compliant with the
PCIe power management specification and supports software control of the
SerDes outputs to allow optimization of power and signal strength in a
system. Furthermore, the SerDes block supports loop-back modes and
advanced reporting of error conditions, which enables efficient
management of the entire system.
© PLX Technology, www.plxtech.com
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10/20/2010, Version 1.0