PEX8613 Datasheet, PDF (1/4 Pages) PLX Technology – PCIe Gen 2, 5.0GT/s 12-lane, 3-port Switch

Version 1.2 2010
Features
ƒ PEX 8613 General Features
o 12-lane, 3-port PCIe Gen 2 switch
- Integrated 5.0 GT/s SerDes
o 19 x 19mm², 324-pin PBGA package
o Typical Power: 1.74 Watts
ƒ PEX 8613 Key Features
o Standards Compliant
- PCI Express Base Specification, r2.0
(backwards compatible w/ PCIe r1.0a/1.1)
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
o High Performance
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 140ns max packet
latency (x4 to x4)
- 2KB Max Payload Size
- Read Pacing (bandwidth throttling)
- Dual cast
o Flexible Configuration
- Registers configurable with strapping
pins, EEPROM, I²C, or host software
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM
o Dual-Host & Fail-Over Support
- Configurable Non-Transparent port
- Moveable upstream port
- Crosslink port capability
o Dual-Clock Domain
- SSC clock isolation
o Quality of Service (QoS)
- Two Virtual Channels
- Eight traffic classes per port
- Weighted round-robin source
port arbitration
o Reliability, Availability, Serviceability
- All ports Hot-Plug capable thru I²C
(Hot-Plug Controller on every port)
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance Monitoring
• Per port payload & header counters
- JTAG AC/DC boundary scan
PEX 8613
PCIe Gen 2, 5.0GT/s 12-lane, 3-port Switch
The ExpressLane^TM PEX 8613 device offers PCI Express switching
capability enabling users to add scalable high bandwidth, non-blocking
interconnection to a wide variety of applications including
workstations, storage systems, communications platforms,
embedded systems, and intelligent I/O modules. The PEX 8613 is
well suited for fan-out, aggregation, and peer-to-peer applications.
High Performance & Low Packet Latency
The PEX 8613 architecture supports packet cut-thru with a maximum
latency of 140ns (x4 to x4). This, combined with large packet memory and
non-blocking internal switch architecture, provides full line rate on all ports
for performance-hungry applications such as servers and switch fabrics.
The low latency enables applications to achieve high throughput and
performance. In addition to low latency, the device supports a max payload
size of 2048 bytes, enabling the user to achieve even higher throughput.
Data Integrity
The PEX 8613 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction as packets
pass through the switch.
Flexible Register & Port Configuration
The PEX 8613’s 3 ports can achieve link up to lane widths of x1, x2, or x4.
Flexible buffer allocation, along with the device's flexible packet flow
control, maximizes throughput for applications where more traffic flows in
the downstream, rather than upstream, direction. Any port can be designated
as the upstream port, which
can be changed dynamically.
x4
x4
The PEX 8613 also provides
several ways to configure its
registers. The device can be
PEX 8613
PEX 8613
NT
configured through
strapping pins, I²C
interface, host software, or
x4 x4
x4 x4
an optional serial EEPROM.
This allows for easy debug
x4
during the development
phase, performance
monitoring during the
PEX 8613
NT
operation phase, and driver
or software upgrade. Figure
1 shows some of the
x4
PEX 8613’s common port
configurations.
Figure 1. Common Port Configurations