PEX8609 Datasheet, PDF (1/4 Pages) PLX Technology – Flexible & Versatile 8-lane 8-port PCI Express Switch

Version 1.4 2010
Features
ƒ PEX 8609 General Features
o 8-lane PCI Express switch
- Integrated 5.0 GT/s SerDes
o Up to 8 configurable ports
o 15 x 15mm², 196-ball PBGA
o Typical Power: 1.60 Watts
ƒ PEX 8609 Key Features
o Standards Compliant
- PCI Express Base Specification r2.0
(Backwards compatible with PCIe
r1.0a/1.1)
- PCI Power Management Spec r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
o Integrated DMA Engine
- Four DMA Channels
- Internal Descriptor Support
- DMA function independent from
transparent switch function
- 64-bit Addressing
- Prefetch Descriptor Mode
- Up to 4.0 GB/s throughput per channel
o Dual-Host & Fail-Over Support
- Configurable Non-Transparent port
(NTB)
- Moveable upstream port
- Crosslink port capability
o High Performance
- Cut-Thru latency: 140ns
- 2KB max payload size
- Read Pacing
- Dual-Cast
o Flexible Configuration
- 8 flexible & configurable ports
(x1 or x4)
- Configurable with strapping pins,
EEPROM, I²C, or Host software
- Lane and polarity reversal
o PCI Express Power Management
- Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
- Device states: D0 and D3_hot
o Spread Spectrum Clock Isolation
- Dual clock domain
o Quality of Service (QoS)
- Two Virtual Channels (VC) per port
- Eight Traffic Classes per port
- Weighted Round-Robin Port & VC
Arbitration
o Reliability, Availability, Serviceability
- All ports Hot-Plug capable thru I²C
(Hot-Plug Controller on every port)
- Data path protection
- Memory (RAM) error correction
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance monitoring
(per port payload & header counters)
PEX 8609
Flexible & Versatile 8-lane 8-port PCI Express^® Switch
The ExpressLane^™ PEX 8609 device offers PCI Express switching capability
enabling users to add scalable high bandwidth non-blocking interconnection to a
wide variety of applications including control planes, communication platforms,
servers, storage systems and embedded systems. The PEX 8609 is well suited for
fan-out, aggregation, peer-to-peer, and intelligent I/O module applications.
Low Packet Latency & High Performance
The PEX 8609 architecture supports packet cut-thru with a maximum latency of
140ns. This, combined with large packet memory and non-blocking internal switch
architecture, provides full line rate on all ports for low-latency applications such as
communications and servers. The low latency enables applications to achieve high
throughput and performance. In addition to low latency, the device supports a max
payload size of 2048 bytes, enabling the user to achieve even higher throughout.
Integrated DMA Engine
The PEX 8609 provides a versatile and powerful DMA engine built in to the device
which can be used as a stand alone DMA engine. The DMA engine removes the
burden resulting from having to move data between devices away from the
processor. This allows the processor to perform computational tasks instead. The
four DMA channels can support high data rate transfers between IO devices
connected to any of the available ports in the PEX8609. Additionally, the DMA
engine in the PEX 8609 can be used to complement the DMA engine in the
processor by providing additional DMA channels for higher performance.
Data Integrity
The PEX 8609 provides end-to-end CRC protection (ECRC) and Poison bit support
to enable designs that require guaranteed error-free packets. PLX also supports
data path parity and memory (RAM) error correction as packets pass through the
switch.
Dual-Host and Fail-Over Support
The PEX 8609 supports full non-transparent bridging (NTB) functionality to allow
implementation of multi-host systems and intelligent I/O modules in applications
which require redundancy support such as communications, storage, and servers.
Non-transparent bridges allow systems to isolate host memory domains by
presenting the processor subsystem as an endpoint rather than another memory
system. Base address registers are used to translate addresses; doorbell registers are
used to send interrupts between the address domains; and scratchpad registers are
accessible from both address domains to allow inter-processor communication.
Interoperability
The PEX 8609 is designed to be fully compliant with the PCI Express Base
Specification r2.0 and is backwards compatible to PCI Express Base Specification
r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and
polarity reversal. Furthermore, the PEX 8609 is designed for Microsoft Vista
compliance. All PLX switches undergo thorough interoperability testing in PLX’s
Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure
compatibility with PCI Express devices in the market.