MGA-43024 Datasheet, PDF (1/18 Pages) AVAGO TECHNOLOGIES LIMITED – 2.4 GHz WLAN Power Amplifier Module

MGA-43024
2.4 GHz WLAN Power Amplifier Module
Data Sheet
Description
Avago Technologies’ MGA-43024 is a fully matched power
amplifier for use in the WLAN band (2401- 2484 MHz). High
linear output power at 5.0 V is achieved through the use
of Avago’s proprietary 0.25 µm GaAs Enhancement-mode
pHEMT process. MGA-43024 is housed in a miniature 5.0
mm × 5.0 mm molded-chip-on-board (MCOB) module
package. A detector is also included on-chip. The compact
footprint coupled with high gain, high linearity and good
efficiency makes the MGA-43024 an ideal choice as a
power amplifier for small cell enterprise WLAN PA applica-
tions.
Component Image
(5.0 × 5.0 × 0.82) mm Package Outline
A_VAGO
43024
YYWW
XXXX
TOP VIEW
Notes:
Package marking provides orientation
and identification
”43024” = Device part number
”YYWW” = Year and work week
”XXXX” = Assembly lot number
Features
• Linear P_out @ EVM =2.5% (802.11n): 27.8 dBm
• Linear P_out with Restricted Band Emission (802.11n) of
-48 dBm @ 2412 MHz: 22.2 dBm
• Linear P_out with Restricted Band Emission (802.11n) of
-48 dBm @ 2462 MHz: 22.2 dBm
• High gain : 40.5 dB
• Fully matched input and output ports
• Built-in detector
• GaAs E-pHEMT Technology ^[1]
• Low-cost small package size: (5.0 × 5.0 × 0.82) mm
• MSL3
• Lead-free/Halogen-free/RoHS compliance
Note:
1. Enhancement mode technology employs positive V_GS, and so
eliminates the need for negative gate voltage associated with
conventional depletion mode devices.
Applications
• Enterprise WLAN access points
• Small cell with embedded WLAN
Pin Configuration
Gnd 1
Gnd 2
NC 3
RFin 4
NC 5
Gnd 6
NC 7
(5.0 × 5.0 × 0.82) mm
21 Gnd
20 Gnd
19 RFout
18 RFout
17 RFout
16 Gnd
15 Gnd
Attention: Observe precautions for
handling electrostatic-sensitive devices.
ESD Machine Model = 60 V
ESD Human Body Model = 400 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Functional Block Diagram
Vdd1 Vdd2
Vdd3
RFin ^{1st Stage 2nd Stage} 3^rd Stage
RFout
Top View
Biasing Circuit
Vc1 Vc2 Vc3 VddBias Vdet