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ACPL-P481 Datasheet, PDF (1/9 Pages) AVAGO TECHNOLOGIES LIMITED – Inverted Logic, High CMR Optocoupler for Intelligent Power Modules and IGBT/MOSFET Gate Drive | |||
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ACPL-P481 and ACPL-W481
Inverted Logic, High CMR Optocoupler for Intelligent
Power Modules and IGBT/MOSFET Gate Drive
Data Sheet
Description
The high-speed ACPL-P481/W481 optocoupler contains
a GaAsP LED, photo detector and a Schmitt trigger that
eliminates the need for external waveform conditioning
circuits.
The totem pole output eliminates the need for a pull-up
resistor. An Intelligent Power Module, Power MOSFET or
IGBT can be driven directly.
Propagation delay difference between devices has been
minimized to maximize inverter efficiency through
reduced switching dead time.
Applications
⢠IPM Interface Isolation
⢠Isolated IGBT/MOSFET Gate Drive
⢠AC and Brushless DC Motor Drives
⢠Industrial Inverters
⢠General Digital Isolation
Functional Diagram
Anode 1
6 VCC
N.C. 2
5 VO
Cathode 3
SHIELD
4 Ground
Note: A 0.1 µF bypass capacitor must be connected between pins 4 and 6.
Truth Table (Positive Logic)
LED
VO
ON
LOW
OFF HIGH
Features
⢠Inverted output type (totem pole output)
⢠Performance Specified for Common IPM Applications
Over Industrial Temperature Range.
⢠Short Maximum Propagation Delays
⢠Minimized Pulse Width Distortion (PWD)
⢠Very High Common Mode Rejection (CMR)
⢠Hysteresis
⢠Available in Stretched SO-6 Package.
⢠Package Clearance/Creepage at 8 mm (ACPL-W481)
⢠Safety Approval: (pending)
â UL Recognized with 3750 Vrms (5000 Vrms for
ACPL-W481) for 1 minute per UL1577.
â CSA Approved.
â IEC/EN/DIN EN 60747-5-5 Approved with VIORM =
891 Vpeak for ACPL-P481 and VIORM = 1140 Vpeak for
ACPL-W481, under option 060.
Specifications
⢠Wide Operating Temperature Range: â40°C to 100°C.
⢠Maximum Propagation Delay tPHL / tPLH = 350 ns
⢠Maximum Pulse Width Distortion (PWD) = 250 ns.
⢠Propagation Delay Difference: Min. â100 ns, Max. 250 ns
⢠Wide Operating VCC Range: 4.5 V to 20 V
⢠20 kV/µs Minimum Common Mode Rejection (CMR) at
VCM = 1000 V.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
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