ACPL-M72T-000E Datasheet, PDF (1/12 Pages) AVAGO TECHNOLOGIES LIMITED – High Speed, Low Power Digital Optocouplers with R2Coupler™ Isolation and AEC-Q100 Grade 1 Qualifi cation

ACPL-M71T and ACPL-M72T
High Speed, Low Power Digital Optocouplers
with R²Coupler™ Isolation and AEC-Q100 Grade 1 Qualification
Data Sheet
Description
The Avago ACPL-M71T and ACPL-M72T are high tem-
perature, digital CMOS optocouplers in SOIC-5 packages.
Suitable for hybrid and electric vehicle applications,
the optocouplers use the latest CMOS IC technology to
achieve outstanding performance and very low power
consumption. All devices are AEC-Q100 compliant and
operate over the –40°C to 125 °C temperature range.
The ACPL-M71T uses a high speed LED, and the ACPL-M72T
uses a low current LED for lower power dissipation. The
high speed ACPL-M71T featuring a 35 ns maximum
propagation delay (I_F =10 mA). The ACPL-M72T optocou-
pler features very low power. With a low 4 mA LED drive
current, ACPL-M72T typical propagation delay is 60 ns.
Each digital optocoupler has a CMOS detector IC, an in-
tegrated photodiode, a high speed transimpedance
amplifier, and a voltage comparator with an output
driver.
Avago R²Coupler isolation products provide the rein-
forced insulation and reliability needed for critical in auto-
motive and high temperature industrial applications
Functional Block Diagram
Features
 5 V CMOS compatible
 Common-Mode Rejection 40kV/s @ V_CM=1000V:
 Wide automotive temperature range: –40°C to 125°C
 Low propagation delay :
– High Speed ACPL-M71T: 26ns @ I_F = 10 mA (Typical)
– Low Power ACPL-M72T: 60ns @ I_F = 4 mA (Typical)
 Worldwide safety approval:
– UL 1577 recognized, 4000 Vrms / 1 min
– CSA approved
– IEC/EN/DIN EN 60747-5-5
 Qualified to AEC-Q100 Grade 1 test guidelines
Applications
 Automotive CANBus communications interface
 Automotive isolated high speed gate drivers for IGBTs
and Power MOSFETs
 High temperature digital signal isolation
 Microcontroller interface
 Digital isolation for A/D and D/A conversion
ACPL-M71T/ACPL-M72T
6 Vdd
Anode ¹
5 _Vo
Cathode 3
4 Gnd
Truth Table
LED Output (V_O)
OFF
H
ON
L
Note: A 0.1 F bypass capacitor must be connected between pins 4 and 6.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.