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ACPL-267XL Datasheet, PDF (1/11 Pages) AVAGO TECHNOLOGIES LIMITED – Low power consumption | |||
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ACPL-267XL, ACPL-268KL, ACPL-560XL,
ACPL-563XL, 5962-08242*
Hermetically Sealed, 3.3V High Speed, High CMR,
Logic Gate Optocouplers
Data Sheet
*See Selection Guide for full matrix of part numbers.
Description
These units are single and dual channel, hermetically
sealed optocouplers. The products are capable of opera-
tion and storage over the full military temperature range
and can be purchased as either standard commercial
product or with full MIL-PRF-38534 Class Level H or K
testing or from DLA Drawing 5962-08242. All devices are
manufactured and tested on a MIL-PRF-38534 certified
line and are included in the DLA Qualified Manufacturers
List QML-38534 for Hybrid Microcircuits.
Truth Table (Positive Logic)
Multichannel Devices
Input
On (H)
Off (L)
Output
L
H
Single Channel DIP
Input
On (H)
Off (L)
On (H)
Off (L)
Enable
H
H
L
L
Output
L
H
H
H
Functional Diagram
Multiple channel devices available
VCC
VE
VOUT
GND
Features
ï· Low power consumption
ï· 3.3V supply voltages
ï· Dual marked with device part number and DLA draw-
ing number
ï· Manufactured and tested on a MIL-PRF-38534
Certified Line
ï· QML-38534, Class H and K
ï· Three hermetically sealed package configurations
ï· Performance guaranteed over full military
temperature range: -55°C to +125°C
ï· High speed: 10 Mbd typical
ï· CMR: > 10,000 V/μs typical
ï· 1500 Vdc withstand test voltage
ï· TTL circuit compatibility
ï· HCPL-260L/060L/263L/063L function compatibility
Applications
ï· Military and aerospace
ï· High reliability systems
ï· Transportation, medical, and life critical systems
ï· Line receiver
ï· Voltage level shifting
ï· Isolated input line receiver
ï· Isolated output line driver
ï· Logic ground isolation
ï· Harsh industrial environments
ï· Isolation for computer, communication, and test
equipment systems
The connection of a 0.1 μF bypass capacitor between V and GND is recommended.
CC
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
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