AS8F512K32_07 Datasheet, PDF (2/23 Pages) Austin Semiconductor – 512K x 32 FLASH FLASH MEMORY ARRAY

FLASH
Austin Semiconductor, Inc.
AS8F512K32
OPERATIONS
Read Mode
A low-level logic signal is applied to CE\ and OE\ pins to
read the output of the AS8F512K32. The CE\ is power control
and is used for device selection.
The delay from stable address to valid output data is the
address access time (tAVQA). The delay from CE\ equals logic
low and stable addresses to valid output data is the chip-en-
sequence transpires. The command register does not fill an
addressable memory location. The register is used to store the
command sequence, along with the address and data needed
by the memory array. Commands are written by setting CE\=VIL
and OE\= VIH and bring WE\ from logic-high to logic-low. Ad-
dresses are latched on the falling edge of WE\ and data is
latched on the rising edge of WE\. Holding WE\ =VIL and
toggling CE\ can be used as an alternative.
able access time (tELQV). The output-enable access time
(tGLQV) is the delay from OE\ =low logic to valid output data,
when CE\ =low logic and addresses are stable for at least tAVQA-
tGLQV.
Read/Reset Command
The read/reset mode is activated by writing either of the
two read/reset command register. The device remains in this
mode until one of the other valid command sequences is input
Standby Mode
Icc supply current is reduced by applying a logic-high on
the CE\ to enter the standby mode. In the standby mode, the
outputs are placed in the high impedance state.
If the device is deselected during erasure or programming,
into the command register. Memory data can be read with stan-
dard microprocessor read-cycle timing in the read mode.
On power up, the device defaults to the read/reset mode.
A read/reset command sequence if not required and memory
data is available.
the device continues to draw active current until the operation
is complete.
Algorithm-Selection Command
The algorithm-selection command allows access to binary
Output Disable
OE\= VIL or CE\=VIH, output from the device is disabled
and the output pins (DQ0 - DQ7) are placed in the high-imped-
ance state.
code that matches the device with the proper programming -
and erase-command operations. After writing the three bus
cycle command sequence, the first byte of the algorithm-selec-
tion code (01) can be read from address XX00. The second
byte of the code (A4) can be read from address XX01. This
Erasure and Programming
mode remains in effect until another valid command sequence
Erasure and programming of the AS8F512K32 are accom- ^{is written to the device.}
plished by writing a sequence of commands using standard
microprocessor write timings. The commands are written to a
command register and input to the command state machine.
The command state machine interprets the command entered
and initiates program, erase, suspend, and resume operations
as instructed. The command state machine acts as the inter-
face between the write-state machine and external chip opera-
tions. The write-state machine controls all voltage generation,
pulse generation, preconditioning and verification of the con-
tents of the memory. Program and block/chip-erase functions
are fully automatic. Once the end of a program or erase opera-
tion has been reached, the device internally resets to the read
mode. If Vcc drops below the low-voltage-detect level (VLKO),
any operation in progress is aborted and the device resets to
the read mode. If a byte-program or chip-erase operation is in
progress, additional program/erase operations are ignored un-
til the operation completes.
Byte-Program Command
Byte-programming is a four-bus-cycle-command sequence.
The first three bus cycles put the device into the program-
setup state. The fourth bus cycle loads the address location
and the data to be programmed into the device. The addresses
are latched on the falling edge of WE\ and the data is latched
on the rising edge of WE\ in the fourth cycle. The raising edge
of WE\ starts the byte-program operation. The embedded
byte-programming function automatically provides needed
voltage and timing to program and verify the cell margin. Any
further commands written to the device during the program
operation are ignored.
Programming can be preformed at any address location in
any order. When erased, all bits are in a logic state 1. Logic 0s
are programmed into the device. Attempting to program logic 1
into a bit that has been previously programmed to logic 0 causes
the internal pulse counter to exceed the pulse-count limit. This
Command Definitions
Operating modes are selected by writing particular address
and data sequences into the command register Command Se-
quence Table . The device will reset to read mode if an incor-
rect address and data value or writing them in the incorrect
sets the exceed-timing-limit indicator (DQ5) to a logic high state.
Only an erase operation can change bits from logic 0 to logic 1.
The status of the device during the automatic program-
ming operation can be monitored for the completion using the
data-polling feature or the toggle-bit feature . See the “opera-
tion status” for the full description.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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