MT5C1009 Datasheet, PDF (1/17 Pages) Austin Semiconductor – 128K x 8 SRAM WITH CHIP & OUTPUT ENABLE

Austin Semiconductor, Inc.
SRAM
MT5C1009
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
FEATURES
• Access Times: 15, 20, 25, 35, 45, 55 and 70 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
C
No. 111
CW No. 112
EC No. 207
ECA No. 208
F
No. 303
DCJ No. 501
SOJ No. 507
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
V_SS 16
32 VCC
31 A15
30 CNEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin Flat Pack (F)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ1
13
DQ2
14
DQ3
15
VSS
16
32
VCC
31
A15
30
NCEC2
29
WE\
28
A13
27
A8
26
A9
25
A11
24
OE\
23
A10
22
CE\
21
DQ8
20
DQ7
19
DQ6
18
DQ5
17
DQ4
32-Pin LCC (ECA)
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS 16
32 VCC
31 A15
30 NCEC2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
4 3 2 1 32 31 30
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE \
23 A10
22 CE1\
21 DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory
applications, this device offers chip enable (CE\) and output
enable (OE\) features. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The devices offer a reduced power standby mode when dis-
abled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
MT5C1009
Rev. 5.5 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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