MT5C1005_05 Datasheet, PDF (1/13 Pages) Austin Semiconductor – 256K x 4 SRAM SRAM MEMORY ARRAY

Austin Semiconductor, Inc.
SRAM
MT5C1005
256K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
A7 1
A8 2
A9 3
A10 4
A11 5
A12 6
A13 7
A14 8
A15 9
A16 10
A17 11
CE\ 12
OE\ 13
Vss 14
28 Vcc
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
20 NC
19 DQ4
18 DQ3
17 DQ2
16 DQ1
15 WE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A7
1
A8
2
A9
3
A12
4
A10
5
A11
6
A13
7
NC
8
A14
9
A15
10
A16
11
A17
12
NC
13
CE\
14
OE\
15
Vss
16
32 Vcc
31 A6
30 A5
29 A2
28 A4
27 A3
26 A1
25 NC
24 NC
23 A0
22 NC
21 DQ4
20 DQ3
19 DQ2
18 DQ1
17 WE\
32-Pin Flat Pack (F)
32-Pin LCC (ECW)
A7
1
A8
2
A9
3
A12
4
A10
5
A11
6
A13
7
NC
8
A14
9
A15
10
A16
11
A17
12
NC
13
CE\
14
OE\
15
Vss
16
32
Vcc
31
A6
30
A5
4 3 2 1 31 32 30
29
A2
28
A4 _{A10 5}
27
A3 A11 6
26
A1 A12 7
25
NC ^{A13 8}
A14 9
24
NC _{A15 10}
23
A0 A16 11
22
NC ^{A17 12}
21
DQ4 ^{CE\ 1 3}
29 A2
28 A4
27 A3
26 A1
25 A0
24 NC
23 NC
22 NC
2 1 DQ4
20
DQ3
19
DQ2
14 15 16 17 18 19 20
18
DQ1
17
WE\
• Package(s)
Ceramic DIP (400 mil)
C
Ceramic Quad LCC (contact factory)ECW
Ceramic LCC
EC
Ceramic Flatpack
F
Ceramic SOJ
DCJ
No. 109
No. 206
No. 207
No. 303
No. 501
• Operating Temperature Ranges
Industrial (-40^oC to +85^oC)
IT
Military (-55^oC to +125^oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
MT5C1005
Rev. 3.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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