MT5C1001_05 Datasheet, PDF (1/13 Pages) Austin Semiconductor – 1M x 1 SRAM SRAM MEMORY ARRAY

SRAM
MT5C1001
Austin Semiconductor, Inc. Limited Availability
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
• Three-state output
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C
No. 109
EC No. 207
F
No. 303
DCJ No. 501
• Operating Temperature Ranges
Industrial (-40^oC to +85^oC)
IT
Military (-55^oC to +125^oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1001
Rev. 2.1 06/05
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
A10 1
A11 2
A12 3
A13 4
A14 5
A15 6
NC 7
A16 8
A17 9
A18 10
A19 11
Q 12
WE\ 13
Vss 14
28 Vcc
27 A9
26 A8
25 A7
24 A6
23 A5
22 A4
21 NC
20 A3
19 A2
18 A1
17 A0
16 D
15 CE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10
1
A11
2
A12
3
NC
4
A13
5
A14
6
A15
7
NC
8
A16
9
A17
10
A18
11
A19
12
NC
13
Q
14
WE\
15
Vss
16
32 Vcc
31 NC
30 A9
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 NC
22 A2
21 NC
20 A1
19 A0
18 D
17 CE\
32-Pin Flat Pack (F)
A10
1
A11
2
A12
3
NC
4
A13
5
A14
6
A15
7
NC
8
A16
9
A17
10
A18
11
A19
12
NC
13
Q
14
WE\
15
Vss
16
32
Vcc
31
NC
30
A9
29
A8
28
A7
27
A6
26
A5
25
A4
24
A3
23
NC
22
A2
21
NC
20
A1
19
A0
18
D
17
CE\
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I_SBC2) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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