MT4C4001J_05 Datasheet, PDF (1/21 Pages) Austin Semiconductor – 1 MEG x 4 DRAM Fast Page Mode DRAM

Austin Semiconductor, Inc.
DRAM
MT4C4001J
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\
(CBR), and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
• Timing
70ns access
80ns access
100ns access
120ns access
MARKING
-7
-8
-10
-12
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC*
Ceramic ZIP
Ceramic SOJ
Ceramic SOJ w/ Cu J-lead
Ceramic Gull Wing
CN
C
ECN
CZ
ECJ
ECJA
ECG
No. 103
No. 104
No. 202
No. 400
No. 504
No. 504A
No. 600
*NOTE: If solder-dip and lead-attach is desired on LCC
packages, lead-attach must be done prior to the solder-
dip operation.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
20-Pin DIP (C, CN)
DQ1 1
DQ2 2
WE\ 3
RAS\ 4
A9 5
A0 6
A1 7
20 Vss
19 DQ4
18 DQ3
17 CAS\
16 OE\
15 A8
14 A7
20-Pin SOJ
(ECJ,ECJA),
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
DQ1
DQ2
WE\
RAS\
A9
1
2
3
4
5
26 Vss
25 DQ4
24 DQ3
23 CAS\
22 OE\
A2 8
A3 9
Vcc 10
13 A6
12 A5
11 A4
20-Pin DIP (CZ)
A0 9
A1 10
A2 11
A3 12
Vcc 13
18 A8
17 A7
16 A6
15 A5
14 A4
OE\ 1
DQ3 3
Vss 5
DQ2 7
RAS\ 9
A0 11
A2 13
Vcc 15
A5 17
A7 19
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles each bit is
uniquely addressed through the 20 address bits which are
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the
first 10 bits and CAS\ the later 10 bits. A READ or WRITE
cycle is selected with the WE\ input. A logic HIGH on WE\
dictates READ mode while a logic LOW on WE\ dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE\ or CAS\, whichever occurs last. If
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)
remain open (High-Z) until the next CAS\ cycle. If WE\ goes
LOW after data reaches the output pin(s), Qs are activated and
retain the selected cell data as long as CAS\ remains low
(regardless of WE\ or RAS\). This LATE WE\ pulse results in
a READ-WRITE cycle. The four data inputs and four data
outputs are routed through four pins using common I/O and
pin direction is controlled by WE\ and OE\. FAST-PAGE-
MODE operations allow faster data operations (READ,
WRITE, or READ-MODIFY-WRITE) within a row address
(A0-A9) defined page boundary. The FAST PAGE MODE
(continued)
MT4C4001J
Rev. 2.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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