MT4C1004J Datasheet, PDF (1/14 Pages) Austin Semiconductor – 4 MEG x 1 DRAM FAST PAGE MODE

AUSTIN SEMICONDUCTOR, INC.
MMTT45CC1100045J 883C
4 M25E6GK xx 14 DSRAM
DRAM
4 MEG x 1 DRAM
FAST PAGE MODE
AVAILABLE AS MILITARY
SPECIFICATONS
• SMD 5962-90622
• MIL-STD-883
FEATURES
• Industry standard x1 pinout, timing, functions and
packages
• High-performance, CMOS silicon-gate process
• Single +5V ±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR),
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with ?W/E a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
• Timing
70ns access
80ns access
100ns access
120ns access
MARKING
-7
-8
-10
-12
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic SOJ
Ceramic ZIP
Ceramic Gull Wing
CN
C
ECN
ECJ
CZ
ECG
No. 101
No. 102
No. 202
No. 504
No. 400
No. 600
GENERAL DESCRIPTION
The MT4C1004J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x1 configu-
ration. During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits which are entered 11
bits (A0 -A10) at a time. /R/A/S is used to latch the first 11 bits
and /C/A/S the latter 11 bits. A READ or WRITE cycle is
selected with the ?W/E input. A logic HIGH on ?W/E dictates
READ mode while a logic LOW on ?W/E dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
PIN ASSIGNMENT (Top View)
18-Pin DIP
20-Pin ZIP
D1
WE 2
RAS 3
*A10 4
A0 5
A1 6
A2 7
A3 8
Vcc 9
18 Vss
17 Q
16 CAS
15 A9
14 A8
13 A7
12 A6
11 A5
10 A4
A9 1
Q3
D5
RAS 7
NC 9
A0 11
A2 13
Vcc 15
A5 17
A7 19
2 CAS
4 Vss
6 WE
8 A10*
10 NC
12 A1
14 A3
16 A4
18 A6
20 A8
20-Pin SOJ
20-Pin LCC
20-Pin Gull Wing
D
1
WE
2
RAS
3
NC
4
*A10
5
26 Vss
25 Q
24 CAS
23 NC
22 A9
A0
9
A1
10
A2
11
A3
12
Vcc
13
18 A8
17 A7
16 A6
15 A5
14 A4
*Address not used for /R/A/S-ONLY REFRESH
falling edge of ?W/E or /C/A/S, whichever occurs last. If ?W/E
goes LOW prior to /C/?A/S going LOW, the output pin remains
open (High-Z) until the next /C/A/S cycle. If ?W/E goes LOW
after data reaches the output pin, Q is activated and retains
the selected cell data as long as /C/A/S remains LOW (regard-
less of ?W/E or /R/A/S). This LATE-?W/E pulse results in a
READ-WRITE cycle. FAST PAGE MODE operations allow
faster data operations (READ, WRITE or READ-MODIFY-
WRITE) within a row-address (A0 -A10) defined page
MT4C1004J 883C
REV. 11/97
DS000021
2-23
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.