AS8F1M32 Datasheet, PDF (1/10 Pages) Austin Semiconductor – 1M x 32 FLASH FLASH MEMORY MODULE

AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
FLASH
AS8F1M32
1M x 32 FLASH
FLASH MEMORY MODULE
FIGURE 1: PIN ASSIGNMENT
(Top View)
68 Lead CQFP
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Processing (MIL-PRF-38534, para 1.2)
• Temperature Range -55^oC to 125^oC
FEATURES
• Fast access times of 90ns, 120ns, and 150ns
• 5.0V ±10%, single power supply operation
• Low power consumption typical: 4µA typical CMOS stand-by
* ICC(active) <120mA for READ/WRITE
• 20 year DATA RETENTION at 125^oC
• 1,000,000 program/erase cycles
• 16 equal sectors of 64 Kbytes each
• Any combination of sectors can be erased
• Group sector protection
• Supports FULL chip erase
• Compatible with JEDEC standards
• Embedded erase and program algorithms
• Data\ polling and toggle bits for detection of program or erase
cycle completion.
• Erase suspend/resume
• Hardware reset pin (RESET\)
• Built in decoupling caps and multiple ground pins for low
noise operation
• Separate power and ground planes to improve noise immunity
OPTION
• Timing
90ns
120ns
150ns
MARKING
-90
-120
-150
• Packages
Ceramic Quad Flat Pack (0.88" sq)
QT
- MAX height .140"
- Stand-off Height .035" min
For more products and information
please visit our web site at
www.austinsemiconductor.com
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I/O1
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GND
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GND
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GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F1M32 is a 32 Mbit, 5.0 volt-
only Flash memory. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. The AS8F1M32
offers an access time of 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention, the device has
separate chip enable (CE\), write enable (WE\) and output enable (OE\)
controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC
single-power-supply FLASH standard. Commands are written to the
command register using standard microprocessor write timings.
Register contents serve as input to an internal state-matching that
controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading
from other FLASH or EPROM devices.
Device programming occurs by executing the program command
sequence. This initiates the Embedded Program algorithm - an internal
algorithm that automatically time the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm - an internal algorithm that
automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper cell
margin.
The host system can detect whether a program or erase operation is
complete by observing the DQ7 (DATA\ Polling) and DQ6 (toggle)
status bits. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
(continued on page 2)
AS8F1M32
Rev. 1.5 09/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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