AS5SS512K36 Datasheet, PDF (1/15 Pages) Austin Semiconductor – 512K x 36 SSRAM Flow-Through SRAM No Bus Latency

Austin Semiconductor, Inc.
SSRAM
AS5SS512K36
512K x 36 SSRAM
Flow-Through SRAM
No Bus Latency
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
FEATURES
• Pin compatible and functionally equivalent to ZBT devices.
• Supports 133MHz bus operations with zero wait states
-Data is transferred on every clock
• Internally self-timed output buffer control to eliminate the need to
use asynchronous OE\
• Registered inputs for Flow-Through operation
• Byte Write capability
• Common I/O architecture
• Fast clock-to-output times
-7.5ns (for 133 MHz device)*
-8.5ns (for 117 MHz device)
• Single 3.3V -5% and +1-% power supply V
DD
• Separate V_DD for 3.3V or 2.5V I/O
• Clock Enable (CEN\) pin to suspend operation
• Synchronous self-timed writes
• Available in 100-pin TSOP package.**
• Burst Capability - linear or interleaved burst order
OPTIONS
• Timing
7.5ns access
8.5ns access
MARKING
-7.5*
-8.5
PIN ASSIGNMENT
(Top View)
100-Pin TSOP (DQ)
• Operating Temperature Ranges
Military (-55^oC to +125^oC)
XT
Industrial (-40^oC to +85^oC)
IT
• Package(s)**
100-pin TSOP
DQ
NOTES:
* 7.5ns speed available with IT option only.
**Contact factory for BGA package interests.
GENERAL DESCRIPTION
The AS5SS512K36 is 3.3V, 512K by 36 Synchronous-Flow-
Through Burst SRAMs, designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion of wait
states. The AS5SS512K36 is equipped with the advanced no bus
latency logic required to enable consecutive Read/Write operations
with data being transferred on every clock cycle. This feature dra-
matically improves the throughput of data through the SRAM,
especially in systems that require frequent Read/Write transitions.
The AS5SS512K36 is pin compatible and functionally equivalent to
ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN\) signal, which when deasserted suspends
operation and extends the previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BWS\a,b,c,d) and a Write Enable (WE\) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Synchronous Chip Enable (CE1\, CE2, CE3\) and an
asynchronous Output Enable (OE\) provide for easy bank selection
and output three-state control. In order to avoid bus contention, the
output drivers are synchronously three-stated during the data portion
of a write sequence.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5SS512K36
Rev. 0.2 04/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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