AS5SP256K36DQ Datasheet, PDF (1/11 Pages) Austin Semiconductor – Plastic Encapsulated Microcircuit 9.0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect

Austin Semiconductor, Inc.
COTS PEM
SSRAM
AS5SP256K36DQ
Plastic Encapsulated Microcircuit
9.0Mb, 256K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
• Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
DQPc
1
DQc
2
DQc
3
VDDQ
4
VSSQ
5
DQc
6
DQc
7
DQc
8
DQc
9
VSSQ
10
VDDQ
11
DQc
12
DQc
13
NC
14
VDD
15
NC
16
VSS
17
DQd
18
DQd
19
VDDQ
20
VSSQ
21
DQd
22
DQd
23
DQd
24
DQd
25
VSSQ
26
VDDQ
27
DQd
28
DQd
29
DQPd
30
SSRAM [SPB]
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
• Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges
80
DQPb
79
DQb
78
DQb
77
VDDQ
76
VSSQ
75
DQb
74
DQb
73
DQb
72
DQb
71
VSSQ
70
VDDQ
69
DQb
68
DQb
67
VSS
66
NC
65
VDD
64
ZZ
63
DQa
62
DQa
61
VDDQ
60
VSSQ
59
DQa
58
DQa
57
DQa
56
DQa
55
VSSQ
54
VDDQ
53
DQa
52
DQa
51
DQPa
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
AS5SP256K36DQ
Rev. 1.8 07/09
Units
ns
ns
ns
DQx, DQPx
1
GENERAL DESCRIPTION
ASI’s AS5SP256K36DQ is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in
multiple temperature screening levels, fabricated using
High Performance CMOS technology and is organized
as a 256K x 36. It integrates address and control
registers, a two (2) bit burst address counter supporting
four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
ASI’s AS5SP256K36DQ includes advanced control
options including Global Write, Byte Write as well as
an Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either
the Address Strobe Processor (ADSP\) or Address
Strobe controller (ADSC\) inputs. Subsequent burst
addresses are generated internally in the system’s burst
sequence control block and are controlled by Address
Advance (ADV\) control input.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.