AS5SP1M36DQ Datasheet, PDF (1/22 Pages) Austin Semiconductor – 36Mb Pipelined Sync SRAM

AUSTIN SEMICONDUCTOR, INC.
SSRAM
Austin Semiconductor, Inc. ^AS5SP1M36DQ
36Mb Pipelined Sync SRAM
FEATURES
• Supports bus operation up to 200 MHz
• Available speed grades are 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O power supply
• Fast clock-to-output times
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
• Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-pin TQFP package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
OPTION
MARKING
Temperature Range
Military Temp (-55^oC to +125^oC) /XT
Industrial (-40^oC to +85^oC)
/IT
Enhanced (-40^oC to +105^oC)
/ET
FIGURE 1: PIN ASSIGNMENT
(Top View)
DQP_C
1
DQC
2
DQc
3
V_DDQ
4
V_SSQ
5
DQC
6
DQC
7
DQC
8
DQC
9
V_SSQ
10
V_DDQ
11
DQC
12
DQC
13
NC
14
V_DD
15
NC
16
V_SS
17
DQD
18
DQD
19
V_DDQ
20
V_SSQ
21
DQD
22
DQD
23
DQD
24
DQD
25
V_SSQ
26
V_DDQ
27
DQD
28
DQD
29
DQPD
30
AS5SP1M36DQ
CY7(1CM144x03A6V)33
(1M x 36)
80
DQPB
79
DQB
78
DQB
77
V_DDQ
76
V_SSQ
75
DQB
74
DQB
73
DQB
72
DQB
71
V_SSQ
70
V_DDQ
69
DQB
68
DQB
67
V_SS
66
NC
65
V_DD
64
ZZ
63
DQA
62
DQA
61
V_DDQ
60
V_SSQ
59
DQA
58
DQA
57
DQA
56
DQA
55
V_SSQ
54
V_DDQ
53
DQA
52
DQA
51
DQPA
SELECTION GUIDE
200MHz 166MH
Unit
MaximumAccessTime
3.2
3.4
ns
MaximumOperatingCurrent
425
375
mA
MaximumCMOSStandbyCurrent
120
120
mA
GENERAL DESCRIPTION
The AS5SP1M36DQ SRAM integrates 1M x 36/2M x 18 and
512K x 72 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK).
The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-
expansion Chip Enables (CE2 and CE3), Burst Control
inputs (ADSC, ADSP, and ADV), Write Enables (BWX
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge
of clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled
by the Advance pin (ADV).
Address, data inputs, and write controls are registered on-
chip to initiate a self-timed Write cycle.This part supports
Byte Write operations (see Pin Descriptions and Truth
Table for further details). Write cycles can be one to two or
four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The AS5SP1M36DQ operates from a +3.3V core power
supply while all outputs may operate with either a +2.5 or
+3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
AS5SP1M36DQ
Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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