AS4LC4M4883C Datasheet, PDF (1/20 Pages) Austin Semiconductor – 4 MEG x 4 DRAM 3.3V, EDO PAGE MODE

AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
DRAM
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
AVAILABLE IN MILITARY
SPECIFICATIONS
• MIL-STD-883
• SMD Planned
PIN ASSIGNMENT (Top View)
24/28-Pin
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• Low power, 1mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR)
HIDDEN
• 2,048-cycle (11 row-, 11 column-addresses)
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum VIH level)
VCC
11
DQ1 22
DQ2 33
/W/E
4₄
/R/A/S ⁵5
NC
6₆
A10
9₈
A0
1₉0
A1
1₁1₀
A2
1₁2₁
A3
1₁3₂
VCC
1₁4₃
2268 VSS
2²5^{7 DQ4}
2²4^{6 DQ3}
2²3^{5 /C/A/S}
2²2^{4 /O/E}
2²1^{3 A9}
1²9^{0 A8}
1¹8^{9 A7}
1¹7^{8 A6}
1¹6^{7 A5}
1¹5^{6 A4}
1¹4^{5 Vss}
OPTIONS
• Timing
60ns access (Contact Factory)
70ns acess
80ns access
• Packages
Ceramic SOJ
Ceramic LCC
Ceramic Gull Wing
KEY TIMING PARAMETERS
MARKING
-6
-7
-8
ECJ
EC
ECG
No. 505
No. 212
No. 603
SPEED
-6
-7
-8
t_RC
110ns
130ns
150ns
t_RAC
60ns
70ns
80ns
t_PC
30ns
35ns
40ns
t_AA
30ns
35ns
40ns
t_CAC
15ns
18ns
20ns
t_CAS
12ns
15ns
20ns
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. The AS4LC4M4 ?R?A/S is used to latch the first 11
bits and ?C?A/S the latter 11 bits. READ and WRITE cycles are
selected with the ?W/E input. A logic HIGH on
?W/E dictates READ mode while a logic LOW on ?W/E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of ?W/E or ?C?A/S, whichever occurs last. If
?W/E goes LOW prior to ?C?A/S going LOW, the output pins
remain open (High- Z) until the next ?C?A/S cycle, regardless
of ?O/E.
A logic HIGH on ?W/E dictates READ mode while a logic
LOW on ?W/E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of ?W/E or /C/A/S,
whichever occurs last. An EARLY WRITE occurs when
?W/E is taken LOW prior to /C/A/S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when ?W/E falls after /C/A/S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
O? E/ . During LATE WRITE or READ-MODIFY-WRITE cycles,
?O/E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping ?O/E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by ?W/E and ?O/E.
FAST PAGE MODE
FAST PAGE operations allow faster data operations
(READ, WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by ?R?A/S
followed by a column-address strobed-inby C? ?A/S. ?C?A/S may
be toggled-in by holding ?R?A/S LOW and strobing-in differ-
ent column-addresses, thus executing faster memory cycles.
Returning R?A/S HIGH terminates the FAST PAGE MODE
of operation.
AS4LC4M4
Rev. 11/97
DS000022
2-73
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.