AS4DDR32M72PBG Datasheet, PDF (1/19 Pages) Austin Semiconductor – 32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

iPEM
2.4Gb SDRAM-DDR
Austin Semiconductor, Inc. AS4DDR32M72PBG
32Mx72 DDR SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
„ DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
„ Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CLK and CLK#)
„ Commands entered on each positive CLK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
„ DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
„ DLL to align DQ and DQS transitions with CLK
„ Four internal banks for concurrent operation
„ Two data mask (DM) pins for masking write data
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Industrial, Enhanced and Military Temperature
Ranges
„ Organized as 32M x 72/80
„ Weight: AS4DDR32M72PBG </= 3.10 grams typical
* This product and or it’s specifications is subject to change without notice.
BENEFITS
„ 40% SPACE SAVINGS
„ Reduced part count
„ Reduced I/O count
• 34% I/O Reduction
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
ConfigurationAddressing
Parameter
Configuration
RefreshCount
RowAddress
BankAddress
ColumnAddress
32Megx72
8Megx16x4Banks
8K
8K(A0ͲA12)
4(BA0ͲBA1)
1K(A0ͲA9)
Monolithic Solution
Integrated MCP Solution
O
11.9
11.9
11.9
11.9
11.9
P
T
I
22.3
O
N
S
Area
I/O
Count
5 x 265mm2 = 1328mm2 Plus
5 x 66 pins = 320 pins
32
800mm2
219 Balls
S
A
V
25
I
N
G
S
40+%
34 %
AS4DDR32M72PBG
Rev. 1.2 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1