S3842P Datasheet, PDF (6/7 Pages) AUK corp – Current Mode PWM Controller

peak inductor current controlled by the voltage at pin1.
S3842P
5. Shutdown Techniques
4.7K
8
V REF
1 _COMP
Shutdown of the S3842 can be
4.7K
S HUT
DO W N
5.00
3
ISENSE
S HUT
DOW N
T O CUR R ENT
S ENS E R ES IS T O R
accomplished by two methods;
either raise pin3 above 1V or pull
pin1 below a voltage two diodes
drops above ground. Either causes
the output of the PWM method
comparator to be high (refer to
block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after
the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be
accomplished by adding an SCR which turn off, allowing the SCR to reset.
6. Open Loop Test
2N2222
4.7K
100K
ERROR _1K
AMP
ADJUST
4.7K
ISENSE
ADJUST
RT
1 COMP
2 Vin
3 _ISENSE
4 RT/CT
V REF ⁵
V cc ⁶
OUTPUT 7
V REF
V cc
0.1uF
0.1uF
1K/1W
OUTPUT
GND ⁸
GROUND
High peak currents associated with capacitive leads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Pin5 in a single point ground. The transistor and 5 ㏀ potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to Pin3.
7. Slope Compensation
0.1u F
V REF 8
RT
R T /CT 4
ISENSE ₃
CT _R1
R2
ISENSE
C
R SEN SE
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide
slope compensation for converters requiring duty
cycle over 50%. Note that capacitor C, forms a
filter with R₂ to suppress the leading edge switch
spikes.
KSI-L006-000
6