ATF16V8CZ_14 Datasheet, PDF (9/26 Pages) ATMEL Corporation – Industry-standard Architecture

ATF16V8CZ
7. Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF16V8CZ architecture. Eight config-
urable macrocells can be configured as a registered output, combinatorial I/O, combinatorial
output, or dedicated input.
The ATF16V8CZ can be configured in one of three different modes. Each mode makes the
ATF16V8CZ look like a different device. Most PLD compilers can choose the right mode auto-
matically. The user can also force the selection by supplying the compiler with a mode selection.
The determining factors would be the usage of register versus combinatorial outputs and dedi-
cated outputs versus outputs with output enable control.
The ATF16V8CZ universal architecture can be programmed to emulate many 20-pin PAL
devices. These architectural subsets can be found in each of the configuration modes described
in the following pages. The user can download the listed subset device JEDEC programming file
to the PLD programmer, and the ATF16V8CZ can be configured to act like the chosen device.
Check with your programmer manufacturer for this capability.
Unused product terms are automatically disabled by the compiler to decrease power consump-
tion. A security fuse, when programmed, protects the content of the ATF16V8CZ. Eight bytes
(64 fuses) of User Signature are accessible to the user for purposes such as storing project
name, part number, revision, or date. The User Signature is accessible regardless of the state of
the security fuse.
Table 7-1. Compiler Mode Selection
Registered
ABEL, Atmel-ABEL
P16C8R
CUPL
LOG/iC
G16V8MS
GAL16V8_R⁽¹⁾
OrCAD-PLD
“Registered”
PLDesigner
P16V8R
Tango-PLD
G16V8R
Notes: 1. Only applicable for version 3.4 or lower.
Complex
P16V8C
G16V8MA
GAL16V8_C7⁽¹⁾
“Complex”
P16V8C
G16V8C
Simple
P16V8AS
G16V8AS
GAL16V8_C8⁽¹⁾
“Simple”
P16V8C
G16V8AS
Auto Select
P16V8
G16V8A
GAL16V8
GAL16V8A
P16V8A
G16V8
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