ATAR080-D_14 Datasheet, PDF (9/68 Pages) ATMEL Corporation – Very Low Power Consumption in Active, Power-down and Sleep Mode

ATAR080-D
Table 1. Interrupt Priority Table
Interrupt
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Priority
lowest
|
|
|
|
|
↓
highest
ROM Address
040h
080h
0C0h
100h
140h
180h
1C0h
1E0h
Interrupt Opcode
C8h (SCALL 040h)
D0h (SCALL 080h)
D8h (SCALL 0C0h)
E8h (SCALL 100h)
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
FCh (SCALL 1E0h)
Function
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52 or BP53
Timer 1 interrupt
SSI interrupt or external hardware interrupt at BP40 or BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at any edge at BP50 or BP51
Voltage monitor (VM) interrupt
Table 2. Hardware Interrupts
Interrupt
INT1
INT2
INT3
INT4
INT6
INT7
Interrupt Mask
Register
Bit
P5CR
P52M1, P52M2
P53M1, P53M2
T1M
T1IM
SISC
SIM
T2CM
T2IM
P5CR
P50M1, P50M2
P51M1, P51M2
VCM
VIM
Interrupt Source
Any edge at BP52
Any edge at BP53
Timer 1
SSI buffer full/empty or BP40/BP43 interrupt
Timer 2 compare match/overflow
Any edge at BP50
Any edge at BP51
External/internal voltage monitoring
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction
(SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The
software triggered interrupt operates exactly like any hardware triggered interrupt. The
SWI instruction takes the top two elements from the expression stack and writes the cor-
responding bits via the I/O bus to the interrupt pending register. Therefore, by using the
SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for
later execution.
Hardware Interrupts
In the ATAR080-D, there are eleven hardware interrupt sources with seven different lev-
els. Each source can be masked individually by mask bits in the corresponding control
registers. An overview of the possible hardware configurations is shown in Table 2.
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4676D–4BMCU–12/04