AT24HC02C_14 Datasheet, PDF (9/19 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

7. Device Addressing
The 2-Kbit EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a
Read or Write operation.
The device address word consists of a mandatory ‘1010’ (Ah) sequence for the first four most significant bits as shown
in Figure 7-1. This is common to all Serial EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits for the EEPROM. These three bits must compare to their
corresponding hard-wired input pins A₂, A₁, and A₀ in order for the part to acknowledge.
The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit is high
and a Write operation is initiated if this bit is low.
Upon a valid compare of the device address with hard-wired input pins A₂, A₁, and A₀, the EEPROM will output a zero. If
a compare is not successfully made, the chip will return to a standby state.
Figure 7-1. Device Address
2K 1 0 1 0 A2 A1 A0 R/W
MSB
LSB
8. Write Operations
Byte Write: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such
as a microcontroller, must terminate the write sequence with a Stop condition. At this time, the EEPROM enters an
internally timed write cycle, t_WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see Figure 9-1 on page 10).
Page Write: The 2-Kbit EEPROM is capable of an 8-byte Page Write.
A Page Write is initiated the same as a Byte Write, but the microcontroller does not send a Stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to seven data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the page write sequence with a Stop condition (see Figure 9-2 on page 10).
The data word address lower three bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight
data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.
Data Security: The Atmel AT24HC02C has a hardware data protection scheme that allows the user to write protect the
upper half of the memory (80h - FFh) when the WP pin is at V_CC.
Atmel AT24HC02C [DATASHEET]
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Atmel-8779B-SEEPROM-AT24HC02C-Datasheet_042013