AT86RF212B_14 Datasheet, PDF (86/212 Pages) ATMEL Corporation – Fully integrated 769 – 935MHz transceiver including

• Bit 4 - AACK_UPLD_RES_FT
Upload reserved frame types within RX_AACK mode.
Table 8-9. AACK_UPLD_RES_FT.
Register Bits
Value Description
AACK_UPLD_RES_FT
0 Upload of reserved frame types is disabled
1⁽¹⁾ Upload of reserved frame types is enabled
Note: 1. If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are
further processed. For those frames, an IRQ_3 (TRX_END) interrupt is generated
if the FCS is valid.
In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are
handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An
IRQ_5 (AMI) interrupt is issued, if the addresses in the received frame match the node’s
addresses.
That means, if a reserved frame passes the third level filter rules, an acknowledgement
frame is generated and transmitted if it was requested by the received frame. If this is
not wanted register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set.
• Bit 1 - AACK_PROM_MODE
The register bit AACK_PROM_MODE enables the promiscuous mode, within the
RX_AACK mode.
Table 8-10. AACK_PROM_MODE.
Register Bits
Value Description
AACK_PROM_MODE
0 Promiscuous mode is disabled
1 Promiscuous mode is enabled
Refer to IEEE 802.15.4-2006 Section 7.5.6.5.
If this register bit is set, every incoming frame with a valid PHR finishes with
IRQ_3 (TRX_END) interrupt even if the third level filter rules do not match or the FCS is
not valid. However, register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set
accordingly.
In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an
acknowledgement frame is generated and transmitted unless disabled by register bit
AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode
instead.
86 _AT86RF212B
42002C–MCU Wireless–08/13