AT80C5112_14 Datasheet, PDF (85/97 Pages) ATMEL Corporation – Hardware Watchdog Timer with Reset-out

External Program Memory
Read Cycle
Figure 37. External Program Memory Read Cycle
ALE
PSEN
PORT 0 INSTR IN
T_LHLL
T_LLAX
T_AVLL
A0-A7
T_LLIV
T_LLPL
T_PLPH
12 T_CLCL
T_PLIV
TPLAZ
T_PXIX
INSTR IN
T_PXAV
T_PXIZ
A0-A7
PORT 2
ADDRESS
OR SFR-P2
T_AVIV
ADDRESS A8-A15
INSTR IN
ADDRESS A8-A15
External Data Memory
Characteristics
Table 69. Symbol Description
Symbol
T_RLRH
T_WLWH
T_RLDV
T_RHDX
T_RHDZ
T_LLDV
T_AVDV
T_LLWL
T_AVWL
T_QVWX
T_QVWH
T_WHQX
T_RLAZ
T_WHLH
Parameter
RD Pulse Width
WR Pulse Width
RD to Valid Data In
Data Hold after RD
Data Float after RD
ALE to Valid Data In
Address to Valid Data In
ALE to WR or RD
Address to WR or RD
Data Valid to WR Transition
Data set-up to WR High
Data Hold after WR
RD Low to Address Float
RD or WR High to ALE high
85 AT8xC5112
4191C–8051–02/08