ATTINY4_14 Datasheet, PDF (83/170 Pages) ATMEL Corporation – Bytes In-System Programmable Flash

Figure 13-1. Analog to Digital Converter Block Schematic
8-BIT DATA BUS
ADMUX
ADCSRB
ADCSRA
ADCL
DECODER
TRIGGER
SELECT
PRESCALER
ADC IRQ
V_CC
ADC3
ADC2
ADC1
ADC0
VREF
8-BIT DAC
INPUT
MUX
CONVERSION LOGIC
-
+
SAMPLE & HOLD
COMPARATOR
13.4
Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power Reduction Regis-
ter, PRR (see “PRR – Power Reduction Register” on page 26).
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as
long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a differ-
ent data channel is selected while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger
Select bits, ADTS in “ADCSRB – ADC Control and Status Register B”. See Table 13-4 on page 93 for a list of the
trigger sources. When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a con-
version is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set
when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger
signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt
is disabled. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be
cleared in order to trigger a new conversion at the next interrupt event.
ATtiny4/5/9/10 [DATASHEET] 83
8127F–AVR–02/2013